Design of crosstalk aware energy harvesting system-on-chip

A crosstalk noise aware design methodology is developed, suitable for advanced energy harvesting systems-on-chip (SoCs). The proposed methodology enables accurate substrate crosstalk modeling via process characterization, Python based layout extraction and RC modeling, providing a reliable design flow for robust integrated circuits (IC) implementation. The SoC’s noise coupling performance degradation is accurately estimated, co-calculating the impact of the package and printed-circuit-board (PCB) design. The proposed design flow is seamlessly integrated into the standard design suite. An energy harvesting SoC is used as a product level vehicle. The system is developed in a 0.18 μm CMOS process. The noise aggressor is a digital Maximum Power Point Tracking (MPPT) block, while the noise victim is a DC-DC boost converter and the input voltage sensor. The proposed crosstalk design flow effectively captures the hardware efficiency values, with 14.6% maximum deviation from experimental results, while the standard methodology presents high deviation up to 51.08%.