A power-efficient variable-length prime factor MDC FFT architecture for high-speed wireless communication applications

In this paper, a variable-size power-efficient two-parallel prime factor MDC FFT architecture is proposed which uses a novel reconfigurable processing element pair (RPEP). The prior reconfigurable FFT approaches merely concentrate on FFT architectures with a wide range of FFT sizes. The processing elements/stages are connected to or disconnected from the architecture to vary the size of the FFT. As a result, the hardware is underutilized when the processing elements are disconnected (unused). In the proposed approach, power reduction and effective utilization of hardware are concentrated rather than increasing the number of FFT sizes. The proposed RPEP structure contains two two-parallel processing element which can be either connected in serial or parallel. If one of the processing elements in the RPEP must be disconnected to reduce the FFT size, then the two two-parallel processing elements in the RPEP are configured as a single four-parallel processing element. Due to parallel processing, the frequency of operation is reduced by half and dynamic power is also reduced significantly. The architecture is designed in UMC 65 nm technology and can be configured in seventeen sizes ranging from 8 to 2048-points. The design occupies 0.67 mm.sq and consumption 17.74 mW power when operated at 100 MHz.