VLSI realization of hybrid fast fourier transform using reconfigurable booth multiplier

A discrete fourier transform (DFT) of a series of samples may be quickly and efficiently computed with the use of a mathematical procedure known as the Fast Fourier Transform (FFT). It is possible to put it into action by using adders and multipliers, which are fundamental components of digital circuits. On the other hand, the traditional FFT algorithms resulted in the highest possible level of hardware usage performance. As a result, the primary emphasis of this work is on the development of a hybrid FFT (HFFT) by means of a reconfigurable booth multiplier (RBM). The HFFT algorithm can be divided into two main stages, such as splitting and recombination stages. In the splitting stage, the input sequence is divided into smaller sub-sequences. The splitting stage of the HFFT algorithm can be implemented using radix-2 butterfly unit (R2BU) structure, which is implemented by series of multistage adders (MSA), subtractors, and RBM units. The HFFT is calculated by developing the R2BU function because, it requires small count of MSA with subtractors imitated by complex twiddle factor multipliers for calculation. The simulations show that the proposed MPIC-FFT used 1330 slice registers, 1.260 ns of delay, and 0.122 watts of power. The simulation results show that the proposed HFFT method resulted in reduced area, delay, and power metrics as compared to conventional FFT approaches.