Design an optimal digital phase lock loop with current-starved ring VCO using CMOS technology

This paper describes the design of an optimal and low power Digital Phase Lock Loop (DPLL). It consumes the 485 mV power using 45 nm CMOS technology on CADENCE Virtuoso software. DPLL used for fast speed, less noise or jitter and large bandwidth with very fast acquisition time in wireless or wire line communication for modulator or demodulator. Clock recover, clock synchronization are the important factor in which PLL used. In digital system and microprocessor the DPLL uses for the clock generation and frequency synthesizer. DPLL consist the phase detector, low pass filter and VCO. The VCO produced oscillations at 8.5 Ghz. The average power dissipation or power consumption of DPLL is 485mV at an input voltage of 2 V. The results show that of the proposed DPLL design used for less power consumption, high speed operations applications.