Review paper: Advanced source and drain technologies for low power CMOS at 22/20 nm node and below

As device dimensions scale, optimization of the source and drain portions of MOSFETs becomes more important in order to reduce parasitic resistance and capacitance, and thus ultimately improve overall device performance. Reduction of parasitic resistance requires careful optimization of dopant incorporation and activation. In current cutting-edge technologies, the source/drain region also plays a key role in improving channel carrier mobility though process-induced strain. Introducing various alloys into NiSi and/or implanting appropriate elements has shown to give significant reduction of the Schottky barrier height between NiSi and Si, thereby improving resistance. In this paper, we review key aforementioned source and drain engineering technologies relevant to the 22/20 nm logic technology node and below.