On measurable side-channel leaks inside ASIC design primitives

Leaks inside semi-custom application-specific integrated circuit design primitives are rigorously investigated. The study is conducted by measuring a dedicated test element group chip with a small magnetic field probe on the chip surface. Measurement targets are standard cells and a memory macro cell. Leaks inside the primitives are focused, as many of conventional countermeasures place measurability boundaries on these primitives. Firstly, it is shown that the current-path leak: a leak based on input-dependent active current path within a standard cell (Takahashi 2012 ; Takahashi and Matsumoto IEICE Electron Express 9:458–463, 2012 ) is measurable. Major gate-level countermeasures [Random Switching Logic (RSL), MDPL, and WDDL] become vulnerable if the current-path leak is considered. Secondly, it is shown that the internal-gate leak: a leak based on non-linear sub-circuit within an XOR cell is measurable. It can be exploited to bias the distribution of the random mask. Thirdly, it is shown that the geometric leak: a leak based on geometric layout of the memory matrix structure is measurable. It is a leak correlated to integer representation (cf. Hamming weight) of the memory address. We also show that a ROM-based countermeasure (dual-rail RSL memory; Hashimoto et al. 2012 ) becomes vulnerable with the geometric leak. A general transistor-level design method to counteract the current-path and internal-gate leaks is also shown.