Architecture design for reliable and reconfigurable FPGA-based GNC computer for deep space exploration

SRAM （static random access memory）-based FPGA （field programmable gate array）, owing to its large capacity, high perfor- mance, and dynamical reconfiguration, has become an attractive platform for SoPC （system on programmable chip） develop- ment. However, as the configuration memory and logic memory of the SRAM-based FPGA are highly susceptible to SEUs （single-event upsets） in deep space, it is a challenge to design and implement a highly reliable FPGA-based system for space- craft, and no practical architecture has been proposed. In this paper, a new architecture for a reliable and reconfigurable FPGA- based computer in a highly critical GNC （guidance navigation and control） system is proposed. To mitigate the effect of an SEU on the system, multi-layer reconfiguration and multi-layer TMR （triple module redundancy） techniques are proposed, with a reliable reconfigurable real-time operating system （SpaceOS） managing the system level fault tolerance of the computer in the architecture. The proposed architecture for the reconfigurable FPGA-based computer has been implemented with COTS （commercial off the shelf） FPGA and has firstly been applied to the GNC system of a circumlunar return and reentry flight ve- hicle. The in-orbit results show that the proposed architecture is capable of meeting the requirements of high reliability and high availability, and can provide the expressive varying functionality and runtime flexibility for an FPGA-based GNC com- puter in deep space.