Synthesizing Hardware from Dataflow Programs: An MPEG-4 Simple Profile Decoder Case Study

The MPEG Reconfigurable Video Coding working group is developing a new library-based process for building the reference codecs of future MPEG standards, which is based on dataflow and uses an actor language called Cal . The paper presents a code generator producing RTL targeting FPGAs for Cal , outlines its structure, and demonstrates its performance on an MPEG-4 Simple Profile decoder. The resulting implementation is smaller and faster than a comparable RTL reference design, and the second half of the paper discusses some of the reasons for this counter-intuitive result.