Very linear open-loop CMOS sample-and-hold structure for high precision and high speed ADCs

This paper presents an improved bottom-plate sampling sample-and-hold (S/H) architecture for high speed and high linearity analog to digital converters (ADCs). The proposed circuit reduces the charge injection employing a switch at the S/H‘s output. The S/H circuit has been laid out in 0.35 um CMOS technology and simulated using standard level 49 SPICE parameters. The simulation result shows that the spurious free dynamic range (SFDR) of 80 dB is achieved up to the sampling frequency of 250 MS/s at nyquist input frequency with 1.6 ( V P - P ) differential output swing which is able to realize an ADC of 14-bits resolution.