On-chip sensor selection for effective speed-binning

Advance in technology nodes of integrated circuit (IC) fabrication has introduced increased variation. This presents new challenges for delay testing. To address this challenge, speed-binning based on on-chip delay sensor measurements has been proposed to supplement current speed binning methods. However, due to limitations such as computational complexity, information property management, and design placement and routing restrictions, sensor placement cannot all be perfect, and therefore not all sensor data are guaranteed to be beneficial for IC delay classification. Therefore, in this paper we proposed an optimization based on genetic algorithm in order to select the most suitable speed-sensors for speed binning. Based on SPICE simulation as well as silicon data collected from on-chip delay sensors in a commercial design using a sub-65 nm process, we showed that optimizing sensor selection can improve speed-binning accuracy. In both experiments, the proposed optimization algorithm demonstrated improvement over using all sensor data. Result showed the proposed method is capable of improving accuracy beyond 94 and 93 % , respectively.