A 1 Gsps and 840 µW fully dynamic asynchronous pipelined binary search ADC

In this paper a very low power asynchronous 5-bit ADC in CMOS 45 nm process technology is described which combines the pipeline and binary search architectures. Due to utilization of dynamic non-linear amplifier, power consumption of the converter is very low. The ADC circuit uses digital calibration technique to update the reference voltages of the comparators. The power consumption of ADC is 840 µW, and the ENOB is 4.05 at 1 Gsps with input signal at the Nyquist rate. At sampling rate of 10 0Msps, the power consumption is reduced to 89 µW and the ENOB is equal to 4.6 again at the Nyquist rate.