FPGA realization of high performance large size computational functions: multipliers and applications

In this paper, efficient design methodologies and systematic approaches for realizing large size signed multipliers based on the use of small-size embedded blocks in FPGAs are presented. Two algorithms, delay table and dynamic programming addition optimizations, are used to efficiently organize the addition of partial products. To demonstrate the effectiveness of our approaches, two large size operand computations are realized using our optimized large size multipliers. These functions are complex multiplication and matrix multiplication. The implementations target Xilinx’ and Altera’s FPGAs. When our approaches are compared to those of traditional techniques, the results show improvements of performance and area usage for both applications.