Impact of stress effect on triple material gate step-FinFET with DC and AC analysis

Step-FinFET is an improvisation in various electrical characteristics with a modified mechanism. The gate length 20 nm, 15 nm, 20 nm has allowed an acceptable driving current and considerable power consumption which longer the battery life. The study consist of electron density, electron velocity, mobility, electric field, and surface potential to relate the improved device performance. The major variation of drain current due to stress effect, tunneling, saturation factor, and minority factor has been investigated. This paper analyzes the parameters like transconductance (Gm), Drain conductance (gd), input capacitance (Cgg), cut off frequency (fT), power consumption, etc., for verifying the RF and analog application. Various short channel effect (SCE) also studied in terms of threshold voltage (Vth), sub-threshold swing (SS), drain induced barrier lowering (DIBL) and On/Off ratio are investigated with different gate length and drain bias. As a result the minimum values of threshold voltage, SS and DIBL calculated for gate length of 15 nm are 0.2426 V, 69 mV/dec, 14.6 mV/V, respectively.