Adjustable passivation of SiO2 trap states in OFETs by an ultrathin CVD deposited polymer coating

Trap state passivation at the interface of oxides with organic materials is crucial for the performance of electronic devices such as FETs or LEDs. Commonly used trap passivation layers such as octadecyltrichlorosilane or hexamethyldisilazane generate a highly hydrophobic surface, severely limiting the range of possible solvents for a subsequent layer deposition from solution. In this study, we investigate the trap passivation functionality of parylene C, known for its excellent encapsulation properties and chemical inertness. Parylene C coatings allow for a broad range of solvents to be used in the subsequent layer deposition. We observed a distinct gate bias stress effect in OFET devices due to a little, but constant seepage of charge through parylene C. The permeability of parylene C can be adjusted by thickness and thermal curing at moderate temperatures (100 °C).