Implementation of a low-cost phase-locked loop clock-recovery module for 40-Gb/s optical receivers
A low‐cost, compact, high‐performance clock‐recovery (CR) module using a new phase‐locked loop (PLL) for 40‐Gb/s optical receivers is successfully designed and implemented. The newly implemented frequency detector in the PLL helps to reduce the current consumption and also extended the frequency‐cap...
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| Veröffentlicht in: | Microwave and optical technology letters 2006-02, Vol.48 (2), p.312-315 |
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| container_title | Microwave and optical technology letters |
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| creator | Woo, Dong Sik Kim, Kang Wook Lim, Sang-Kyu Ko, Jesoo |
| description | A low‐cost, compact, high‐performance clock‐recovery (CR) module using a new phase‐locked loop (PLL) for 40‐Gb/s optical receivers is successfully designed and implemented. The newly implemented frequency detector in the PLL helps to reduce the current consumption and also extended the frequency‐capture range. The implemented PLL clock‐recovery module demonstrates advantages over the conventional open‐loop type clock‐recovery module with a DR filter by significantly improving clock jitter, thus reducing overall module cost, and allowing the possibility of providing a proper clock signal in the case of temporary loss of NRZ input signals. The CR module exhibits error‐free operation during a 30‐min BER test with a time‐division‐multiplexing (TDM) 40‐Gb/s transmission system. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 312–315, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21335 |
| doi_str_mv | 10.1002/mop.21335 |
| format | Article |
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The newly implemented frequency detector in the PLL helps to reduce the current consumption and also extended the frequency‐capture range. The implemented PLL clock‐recovery module demonstrates advantages over the conventional open‐loop type clock‐recovery module with a DR filter by significantly improving clock jitter, thus reducing overall module cost, and allowing the possibility of providing a proper clock signal in the case of temporary loss of NRZ input signals. The CR module exhibits error‐free operation during a 30‐min BER test with a time‐division‐multiplexing (TDM) 40‐Gb/s transmission system. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 312–315, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). 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Opt. Technol. Lett</addtitle><description>A low‐cost, compact, high‐performance clock‐recovery (CR) module using a new phase‐locked loop (PLL) for 40‐Gb/s optical receivers is successfully designed and implemented. The newly implemented frequency detector in the PLL helps to reduce the current consumption and also extended the frequency‐capture range. The implemented PLL clock‐recovery module demonstrates advantages over the conventional open‐loop type clock‐recovery module with a DR filter by significantly improving clock jitter, thus reducing overall module cost, and allowing the possibility of providing a proper clock signal in the case of temporary loss of NRZ input signals. The CR module exhibits error‐free operation during a 30‐min BER test with a time‐division‐multiplexing (TDM) 40‐Gb/s transmission system. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 312–315, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21335</description><subject>40 Gb/s</subject><subject>clock and data recovery (CDR)</subject><subject>clock recovery (CR)</subject><subject>jitter</subject><subject>phase-locked loop (PLL)</subject><issn>0895-2477</issn><issn>1098-2760</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><recordid>eNp1kMtOwzAQRS0EEqWw4A-8ZeFmYidxskQVtJVKW4kCS8vxQ4QmdWQHSv-elAI7VqO5Onc0OghdxzCKAWjUuHZEY8bSEzSIocgJ5RmcogHkRUpowvk5ugjhDQAY53SAylnT1qYx2052ldtiZ7HEtdsR5UKH21cZDKmd2hjdp67F6rAQb5T7MH6PG6ffa4Ot8zgBMimjgF3bVUrWuGdM1UPhEp1ZWQdz9TOH6On-bj2ekvlyMhvfzoliwFPS_6wU5LmWhZZpWmgFhuksYSmUpVal1NxyWjLJ-9Qqyy0YbRNacKnjRAIbopvjXeVdCN5Y0fqqkX4vYhAHOaKXI77l9Gx0ZHdVbfb_g-JhufptkGOjCp35_GtIvxEZZzwVL4uJmD_D43q6WoiMfQFqDXdd</recordid><startdate>200602</startdate><enddate>200602</enddate><creator>Woo, Dong Sik</creator><creator>Kim, Kang Wook</creator><creator>Lim, Sang-Kyu</creator><creator>Ko, Jesoo</creator><general>Wiley Subscription Services, Inc., A Wiley Company</general><scope>BSCLL</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>200602</creationdate><title>Implementation of a low-cost phase-locked loop clock-recovery module for 40-Gb/s optical receivers</title><author>Woo, Dong Sik ; Kim, Kang Wook ; Lim, Sang-Kyu ; Ko, Jesoo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c3075-335cc088da9da559dc0e3d64350bbdcbad7f72b3a73d6fcf7f0edf4297ad14a03</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2006</creationdate><topic>40 Gb/s</topic><topic>clock and data recovery (CDR)</topic><topic>clock recovery (CR)</topic><topic>jitter</topic><topic>phase-locked loop (PLL)</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Woo, Dong Sik</creatorcontrib><creatorcontrib>Kim, Kang Wook</creatorcontrib><creatorcontrib>Lim, Sang-Kyu</creatorcontrib><creatorcontrib>Ko, Jesoo</creatorcontrib><collection>Istex</collection><collection>CrossRef</collection><jtitle>Microwave and optical technology letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Woo, Dong Sik</au><au>Kim, Kang Wook</au><au>Lim, Sang-Kyu</au><au>Ko, Jesoo</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Implementation of a low-cost phase-locked loop clock-recovery module for 40-Gb/s optical receivers</atitle><jtitle>Microwave and optical technology letters</jtitle><addtitle>Microw. Opt. Technol. Lett</addtitle><date>2006-02</date><risdate>2006</risdate><volume>48</volume><issue>2</issue><spage>312</spage><epage>315</epage><pages>312-315</pages><issn>0895-2477</issn><eissn>1098-2760</eissn><abstract>A low‐cost, compact, high‐performance clock‐recovery (CR) module using a new phase‐locked loop (PLL) for 40‐Gb/s optical receivers is successfully designed and implemented. The newly implemented frequency detector in the PLL helps to reduce the current consumption and also extended the frequency‐capture range. The implemented PLL clock‐recovery module demonstrates advantages over the conventional open‐loop type clock‐recovery module with a DR filter by significantly improving clock jitter, thus reducing overall module cost, and allowing the possibility of providing a proper clock signal in the case of temporary loss of NRZ input signals. The CR module exhibits error‐free operation during a 30‐min BER test with a time‐division‐multiplexing (TDM) 40‐Gb/s transmission system. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 312–315, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21335</abstract><cop>Hoboken</cop><pub>Wiley Subscription Services, Inc., A Wiley Company</pub><doi>10.1002/mop.21335</doi><tpages>4</tpages></addata></record> |
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| ispartof | Microwave and optical technology letters, 2006-02, Vol.48 (2), p.312-315 |
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| source | Wiley Online Library Journals Frontfile Complete |
| subjects | 40 Gb/s clock and data recovery (CDR) clock recovery (CR) jitter phase-locked loop (PLL) |
| title | Implementation of a low-cost phase-locked loop clock-recovery module for 40-Gb/s optical receivers |
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