Improved performance of fast acquisition PLL synthesizer with N-stage cycle swallower

The PLL frequency synthesizer with an N‐stage cycle swallower (NSCS) is one of the fastest frequency switching synthesizers. The synthesizer, however, requires many stages in the NSCS to obtain accurate output frequencies. In this paper, to obtain both more accurate output frequencies with a few stages and a higher speed acquisition time, we propose two methods for improving NSCS switching operation. First, by allowing the NSCS output frequency to be variable a large range of choices in the division ratios becomes available in the NSCS. The proposed synthesizer has the output frequency of deviation within 0.0003 ppm when the 3‐stage cycle swallower is employed. Second, by temporarily increasing the expected amount of the variation in the output frequency, the acquisition time of the NSCS synthesizer can be improved. Experimental results confirm that the proposed technique results in a shortened acquisition time.