Design aspects and analysis of SDH equipment clocks

Network synchronization has gained increasing attention since the introduction of the Synchronous Digital Hierarchy (SDH), as network synchronization performance due to the SDH‐internal bit rate adaptation technique have a major impact on the phase transfer characteristic of SDH‐based networks. Excessive jitter or wander may result in bit errors or frame slips within digital exchanges. This paper discusses the requirements with respect to SDH Equipment Clocks (SEC), which are the basis for improved network synchronization. Two parameters have a significant impact on the phase error generated by the clock: the oscillator performance and the phase detector characteristic. This paper proposes a synthesizer‐based PLL structure employing a fixed frequency highly stable oscillator. A novel approach for an all‐digital phase detector provides enhanced resolution, thereby reducing the phase error. Analytical and simulation results demonstrate the feasibility of this approach.