A system-on-a-chip for real-time software digital media processing

In this paper the authors propose a new system‐on‐a‐chip architecture for image processing that achieves both good processing performance and ease of software development. The architecture consists of three types of programmable processors running in parallel: a RISC CPU for bit string processing, a VLIW CPU for two‐dimensional pixel array processing, and a data transfer processor. The data transfer processor provides a function for transferring small regions in the two‐dimensional pixel array for which addresses change discretely to a data cache while converting them to continuous address data. As a result, the data cache hit rate with respect to the accesses to the small screen regions, which is used frequently in image processing, is greatly improved from around 75% to almost 100%. The authors implemented their architecture in an LSI and ran a performance evaluation using digital television decoder software and an optimized C compiler. The results confirmed that processing performance increased threefold with a 22% rise in the packaging die area. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 89(8): 51–59, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20288