Analysis of photocurrents in low-temperature polysilicon thin-film transistors and the use of simulation to design LDD devices

Design rules are presented for the suppression of photocurrents generated in the depletion layers of the channel/drain junction regions of low‐temperature poly‐Si thin‐film transistors (TFTs). Device simulation based on modeling the behavior of the density of states in a low‐temperature poly‐Si TFT was used to find the width of the junction depletion layer. These simulations show that in order to suppress photocurrents to below 6 pA, the LDD region must have a sheet resistance in the range of 30 and 70kΩ/□, which forces its length to exceed 1 µm. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 86(11): 29–36, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10021