A novel theory on parallel repeater-insertion methodologies for long on-chip interconnects

SUMMARY Repeaters are now widely used to enhance the performance of long on‐chip interconnects in CMOS devices. For RC‐as well as RLC‐modeled interconnects, parallel repeaters (PRs) have proved to be superior to serial ones. In a previous work, a new regeneration technique, named variable‐segment, was proven to outperform other existing regeneration techniques including variable‐repeater techniques. In this paper, an approximate analytical delay model is presented for both the variable‐repeater and variable‐segment parallel regeneration techniques. This model is used to confirm the optimality of our design and is built based on first and second‐moment transfer functions, which take into account the inductive effects of interconnects. HSpice electrical and C + +/MATLAB simulations are conducted to assess the performance of the proposed optimization methodology using 0.25‐µm CMOS technology. The mathematical simulation results are remarkably in agreement with those obtained from electrically simulated variable‐repeater and variable‐segment structures which are used in this work to regenerate interconnect lengths ranging from 0.1 to 10 cm. This work is part of a first‐of‐its‐kind global theory on PRs in repeater‐insertion methodologies for long on‐chip interconnects. This theory aims at exploring the different degrees of freedom in interconnect modeling as well as repeater type and design parameters. Copyright © 2011 John Wiley & Sons, Ltd. Repeaters are now widely used to enhance the performance of long on‐chip interconnects in CMOS devices. For RC‐as well as RLC‐modeled interconnects, parallel repeaters have proved to be superior to serial ones. In a previous work, a new regeneration technique, named variable‐segment, was proven to outperform other existing regeneration techniques including variable‐repeater techniques. In this paper, an approximate analytical delay model is presented for both the variable‐repeater and variable‐segment parallel regeneration techniques. This model is used to confirm the optimality of our design and is built based on first and second‐moment transfer functions, which take into account the inductive effects of interconnects. HSpice electrical and C++/MATLAB simulations are conducted to assess the performance of the proposed optimization methodology using 0.25 micron CMOS technology. The mathematical simulation results are remarkably in agreement with those obtained from electrically‐simulated variable‐repeater and variable‐segm