Low‐Power Computing: Vertical‐Tunneling Field‐Effect Transistor Based on WSe 2 ‐MoS 2 Heterostructure with Ion Gel Dielectric (Adv. Electron. Mater. 7/2020)

Low‐Power Computing: Vertical‐Tunneling Field‐Effect Transistor Based on WSe 2 ‐MoS 2 Heterostructure with Ion Gel Dielectric (Adv. Electron. Mater. 7/2020)

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Veröffentlicht in:Advanced electronic materials 2020-07, Vol.6 (7)
Hauptverfasser: Jeon, Hyun Bae, Shin, Gwang Hyuk, Lee, Khang June, Choi, Sung‐Yool
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container_issue 7
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container_title Advanced electronic materials
container_volume 6
creator Jeon, Hyun Bae
Shin, Gwang Hyuk
Lee, Khang June
Choi, Sung‐Yool
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doi_str_mv 10.1002/aelm.202070030
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title Low‐Power Computing: Vertical‐Tunneling Field‐Effect Transistor Based on WSe 2 ‐MoS 2 Heterostructure with Ion Gel Dielectric (Adv. Electron. Mater. 7/2020)
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