Li Intercalation Effects on Interface Resistances of High‐Speed and Low‐Power WSe 2 Field‐Effect Transistors

Van der Waals (vdW) layered materials are promising channel materials for next‐generation field‐effect transistors (FETs). However, in vdW layered‐material FETs, the Schottky barrier and tunnel barrier at the vdW interfaces significantly reduce the electron injection efficiencies at electrical conta...

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Veröffentlicht in:Advanced functional materials 2020-11, Vol.30 (45)
Hauptverfasser: Shin, Yong Seon, Lee, Kiyoung, Duong, Dinh Loc, Kim, Jun Seok, Kang, Won Tae, Kim, Ji Eun, Won, Ui Yeon, Lee, Ilmin, Lee, Hyangsook, Heo, Jinseong, Lee, Young Hee, Yu, Woo Jong
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Sprache:eng
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Zusammenfassung:Van der Waals (vdW) layered materials are promising channel materials for next‐generation field‐effect transistors (FETs). However, in vdW layered‐material FETs, the Schottky barrier and tunnel barrier at the vdW interfaces significantly reduce the electron injection efficiencies at electrical contacts, thereby limiting the development of high‐speed and low‐power FETs. This study demonstrates that intercalated lithium (Li) ions at vdW interfaces lower the Schottky and tunnel barriers at the electrical contacts of multilayer tungsten diselenide FETs owing to the low potential energy of Li and the mild electron doping from intercalation, thus decreasing the resistance at the vdW interfaces and enhancing the current flow and field‐effect mobility. Compared with before‐Li intercalation, the multilayer WSe 2 planar FET demonstrates ≈1000 times higher current ( I DS = 17.8 μA) at V GS = 50 V, ≈110 times higher maximum field‐effect mobility ( μ FE = 97.67 cm 2 V −1 s −1 ), and ≈1000 times higher on/off current ratio (on/off ratio = ≈10 7 ). Furthermore, in multilayer WSe 2 vertical FETs with vdW heterostructures having a structural strength of approximately the same as the current density, the intercalated Li ions at the graphene/WSe 2 vdW interfaces additionally improves the current density and the vertical mobility by ≈20 times (1.00 A cm −2 ) and 10 times (2.52 × 10 −4 cm 2 V −1 s −1 ), respectively. This study establishes a method to reduce the resistance at vdW interfaces for developing high‐speed and low‐power multilayer vdW material FETs.
ISSN:1616-301X
1616-3028
DOI:10.1002/adfm.202003688