Exploration of High‐Pressure Annealing and Microwave Annealing in Palladium Germano‐Silicide Formation for Si 0.8 Ge 0.2 ‐Based Complementary Metal‐Oxide–Semiconductor Transistors

In this study, forming palladium germano‐silicide on Si 0.8 Ge 0.2 ‐based complementary metal‐oxide semiconductor (CMOS) transistors by high‐pressure annealing compared to microwave annealing is investigated. Boron‐doped Si 0.8 Ge 0.2 layers are epitaxially grown on n‐type Si wafers, achieving an initial boron concentration of 5 × 10 15 cm −3 , which increase to ≈6 × 10 20 cm −3 after microwave annealing, reducing sheet resistance. Palladium is deposited using electron beam evaporation to form a 15 nm layer on Si 0.8 Ge 0.2 (200 nm)/Si (100) substrates. High‐pressure annealing is conducted from 300 to 500 °C in N 2 ambiance at 5 kg cm −3 , while microwave annealing is performed at 5.8 GHz and 1800–3000 W for 100 s. X‐ray diffractometer confirms high‐intensity Pd 2 Si phase formation, but scanning electron microscope and atomic force microscope reveal increased surface roughness and clustering after annealing. Sheet resistance increases from 10.35 Ω sq −1 (unannealed) to 131.8 Ω sq −1 (high‐pressure annealing at 300 °C) and 85.8 Ω sq −1 (microwave annealing at 1800 W). In these results, the trade‐offs between annealing methods and metal choices for achieving low contact resistance and Schottky barrier heights in p‐type Si 0.8 Ge 0.2 CMOS circuits are highlighted.