Real-time Digital RF Emulation -- II: A Near Memory Custom Accelerator

A near memory hardware accelerator, based on a novel direct path computational model, for real-time emulation of radio frequency systems is demonstrated. Our evaluation of hardware performance uses both application-specific integrated circuits (ASIC) and field programmable gate arrays (FPGA) methodo...

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Hauptverfasser: Mukherjee, Mandovi, Mao, Xiangyu, Rahman, Nael, DeLude, Coleman, Driscoll, Joe, Sharma, Sudarshan, Behnam, Payman, Kamal, Uday, Woo, Jongseok, Kim, Daehyun, Khan, Sharjeel, Tong, Jianming, Seo, Jamin, Sinha, Prachi, Swaminathan, Madhavan, Krishna, Tushar, Pande, Santosh, Romberg, Justin, Mukhopadhyay, Saibal
Format: Artikel
Sprache:eng
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Zusammenfassung:A near memory hardware accelerator, based on a novel direct path computational model, for real-time emulation of radio frequency systems is demonstrated. Our evaluation of hardware performance uses both application-specific integrated circuits (ASIC) and field programmable gate arrays (FPGA) methodologies: 1). The ASIC testchip implementation, using TSMC 28nm CMOS, leverages distributed autonomous control to extract concurrency in compute as well as low latency. It achieves a $518$ MHz per channel bandwidth in a prototype $4$-node system. The maximum emulation range supported in this paradigm is $9.5$ km with $0.24$ $\mu$s of per-sample emulation latency. 2). The FPGA-based implementation, evaluated on a Xilinx ZCU104 board, demonstrates a $9$-node test case (two Transmitters, one Receiver, and $6$ passive reflectors) with an emulation range of $1.13$ km to $27.3$ km at $215$ MHz bandwidth.
DOI:10.48550/arxiv.2406.08714