A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping

A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping

This article is withdrawn because the co-authors are not in favor of publication.

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Bibliographische Detailangaben
Hauptverfasser: Roymohapatra, Sitansusekhar, Gore, Ganesh R, Yadav, Akanksha, Patil, Mahesh B, Rengarajan, Krishnan S, Iyer, Subhramanian S, Baghini, Maryam Shojaei
Format: Artikel
Sprache:eng
Schlagworte:
Computer Science - Hardware Architecture
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Zusammenfassung:This article is withdrawn because the co-authors are not in favor of publication.
DOI:10.48550/arxiv.1903.11264