Simulating spin systems on IANUS, an FPGA-based computer
We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is co...
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| Veröffentlicht in: | arXiv.org 2007-04 |
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| creator | Belletti, F Cotallo, M Cruz, A Fernández, L A Gordillo, A Maiorano, A Mantovani, F Marinari, E Martín-Mayor, V Muñoz-Sudupe, A Navarro, D Pérez-Gaviro, S Ruiz-Lorenzo, J J Schifano, S F Sciretti, D Tarancón, A Tripiccione, R Velasco, J L |
| description | We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O(100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system. |
| doi_str_mv | 10.48550/arxiv.0704.3573 |
| format | Article |
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We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system.</description><subject>Algorithms</subject><subject>Computer Science - Hardware Architecture</subject><subject>Computer simulation</subject><subject>Hardware description languages</subject><subject>Microprocessors</subject><subject>Monte Carlo simulation</subject><subject>Physics - Disordered Systems and Neural Networks</subject><issn>2331-8422</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2007</creationdate><recordtype>article</recordtype><sourceid>ABUWG</sourceid><sourceid>AFKRA</sourceid><sourceid>AZQEC</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><sourceid>GOX</sourceid><recordid>eNotj99LwzAUhYMgOObefZKAr7YmublN8liGm4OhwuZzuWsz6Vh_2LTi_ns759OBw-HjfIzdSRFriyieqPspv2NhhI4BDVyxiQKQkdVK3bBZCAchhEqMQoQJs5uyGo7Ul_UnD21Z83AKva8Cb2q-Sl8_No-car54X6bRjoIveN5U7dD77pZd7-kY_Ow_p2y7eN7OX6L123I1T9cRoZSRJsilR6KdB2WE1IYsSLR5AqZwBbi9QsKx97lXxgrrnLOioII0Yu4dTNn9BftnlbVdWVF3ys522dluHDxcBm3XfA0-9NmhGbp6vJSpEWddooWEXzofT8A</recordid><startdate>20070426</startdate><enddate>20070426</enddate><creator>Belletti, F</creator><creator>Cotallo, M</creator><creator>Cruz, A</creator><creator>Fernández, L A</creator><creator>Gordillo, A</creator><creator>Maiorano, A</creator><creator>Mantovani, F</creator><creator>Marinari, E</creator><creator>Martín-Mayor, V</creator><creator>Muñoz-Sudupe, A</creator><creator>Navarro, D</creator><creator>Pérez-Gaviro, S</creator><creator>Ruiz-Lorenzo, J J</creator><creator>Schifano, S F</creator><creator>Sciretti, D</creator><creator>Tarancón, A</creator><creator>Tripiccione, R</creator><creator>Velasco, J L</creator><general>Cornell University Library, arXiv.org</general><scope>8FE</scope><scope>8FG</scope><scope>ABJCF</scope><scope>ABUWG</scope><scope>AFKRA</scope><scope>AZQEC</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>HCIFZ</scope><scope>L6V</scope><scope>M7S</scope><scope>PIMPY</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>PRINS</scope><scope>PTHSS</scope><scope>AKY</scope><scope>GOX</scope></search><sort><creationdate>20070426</creationdate><title>Simulating spin systems on IANUS, an FPGA-based computer</title><author>Belletti, F ; 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| subjects | Algorithms Computer Science - Hardware Architecture Computer simulation Hardware description languages Microprocessors Monte Carlo simulation Physics - Disordered Systems and Neural Networks |
| title | Simulating spin systems on IANUS, an FPGA-based computer |
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