Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits

Electromigration is caused by high current density stressin metallization patterns and is a major source of break-down in electronic devices. It is therefore an importantreliability issue to verify current densities within allstressed metallization patterns. In this paper we propose anew methodology for hierarchical verification of currentdensities in arbitrarily shaped analog circuit layouts,including a quasi-3D model to verify irregularities suchas vias. Our approach incorporates thermal simulationdata to account for the temperature dependency of electromigration. The described methodology, which can beintegrated into any IC design flow as a design rule check(DRC), has been successfully tested and verified in commercial design flows.