A new area and shape function estimation technique for VLSI layouts

A new area and shape function estimation technique for VLSI layouts

Area estimation of IC layouts has become an important requirement for early design and top-down chip planning tools. Especially the relation of area and aspect ratio (shape function) is necessary for chip planning. Statistical models have been published with good results for standard cell blocks wit...

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Bibliographische Detailangaben
1. Verfasser: Zimmerman, Gerhard
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Applied computing > Physical sciences and engineering > Engineering
Hardware > Electronic design automation > Physical design (EDA) > Partitioning and floorplanning
Hardware > Hardware validation > Functional verification > Simulation and emulation
Hardware > Very large scale integration design
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Beschreibung
Zusammenfassung:Area estimation of IC layouts has become an important requirement for early design and top-down chip planning tools. Especially the relation of area and aspect ratio (shape function) is necessary for chip planning. Statistical models have been published with good results for standard cell blocks with near unity aspect ratios. This paper describes a new model for the prediction of shape functions for aspect ratios up to 1:5. The model is based on the shape and connectivity of adjacent cells. It can be used for many different design styles and has been tested for standard cell blocks and for the placement of general cells. Categories: 6, 9
DOI:10.5555/285730.285739