A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist

This paper presents a new bit-interleaving 11T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to mitigate the leakage and variation and improve the Write-ability in deep sub-100nm technology. Measurement results from a 4 Kb test chip implemented in 40 nm General Purpose (40G...

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Hauptverfasser:	Chiu, Yi-Wei, Hu, Yu-Hao, Tu, Ming-Hsien, Zhao, Jun-Kai, Jou, Shyh-Jye, Chuang, Ching-Te
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied computing > Physical sciences and engineering > Electronics Hardware > Hardware validation Hardware > Integrated circuits > Semiconductor memory > Static memory
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creator	Chiu, Yi-Wei Hu, Yu-Hao Tu, Ming-Hsien Zhao, Jun-Kai Jou, Shyh-Jye Chuang, Ching-Te
description	This paper presents a new bit-interleaving 11T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to mitigate the leakage and variation and improve the Write-ability in deep sub-100nm technology. Measurement results from a 4 Kb test chip implemented in 40 nm General Purpose (40GP) CMOS technology operates for VDD down to 0.32 V (~0.69X of threshold voltage) with VDDMIN limited by Read operation. The measured maximum operation frequency is 3.5 MHz (16.5 MHz) at 0.32 V (0.38 V) with total power consumption of 15.2 μW (27.2 μW) at 25 °C.
doi_str_mv	10.5555/2648668.2648683
format	Conference Proceeding
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Measurement results from a 4 Kb test chip implemented in 40 nm General Purpose (40GP) CMOS technology operates for VDD down to 0.32 V (~0.69X of threshold voltage) with VDDMIN limited by Read operation. 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identifier	ISBN: 1479912352
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source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Applied computing -- Physical sciences and engineering -- Electronics Hardware -- Hardware validation Hardware -- Integrated circuits -- Semiconductor memory -- Static memory
title	A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist
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