Input vector monitoring on line concurrent BIST based on multilevel decoding logic

Input Vector Monitoring Concurrent Built-In Self Test (BIST) schemes provide the capability to perform testing while the Circuit Under Test (CUT) operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. In this paper a novel input vector monitoring c...

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1. Verfasser:	Voyiatzis, Ioannis
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Hardware > Electronic design automation > Physical design (EDA) Hardware > Emerging technologies Hardware > Hardware test Hardware > Robustness Hardware > Very large scale integration design
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creator	Voyiatzis, Ioannis
description	Input Vector Monitoring Concurrent Built-In Self Test (BIST) schemes provide the capability to perform testing while the Circuit Under Test (CUT) operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. In this paper a novel input vector monitoring concurrent BIST scheme is presented, that reduces considerably the imposed hardware overhead compared to previously proposed schemes.
doi_str_mv	10.5555/2492708.2493016
format	Conference Proceeding
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identifier	ISBN: 3981080181
ispartof	Proceedings of the Conference on Design, Automation and Test in Europe, 2012, p.1251-1256
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source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Hardware -- Electronic design automation -- Physical design (EDA) Hardware -- Emerging technologies Hardware -- Hardware test Hardware -- Robustness Hardware -- Very large scale integration design
title	Input vector monitoring on line concurrent BIST based on multilevel decoding logic
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