Input vector monitoring on line concurrent BIST based on multilevel decoding logic

Input vector monitoring on line concurrent BIST based on multilevel decoding logic

Input Vector Monitoring Concurrent Built-In Self Test (BIST) schemes provide the capability to perform testing while the Circuit Under Test (CUT) operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. In this paper a novel input vector monitoring c...

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Bibliographische Detailangaben
1. Verfasser: Voyiatzis, Ioannis
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Hardware > Electronic design automation > Physical design (EDA)
Hardware > Emerging technologies
Hardware > Hardware test
Hardware > Robustness
Hardware > Very large scale integration design
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Beschreibung
Zusammenfassung:Input Vector Monitoring Concurrent Built-In Self Test (BIST) schemes provide the capability to perform testing while the Circuit Under Test (CUT) operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. In this paper a novel input vector monitoring concurrent BIST scheme is presented, that reduces considerably the imposed hardware overhead compared to previously proposed schemes.
DOI:10.5555/2492708.2493016