Cellular scan test generation for sequential circuits

In this paper, we re-examine the concept of test machine embedding and present a new test machine architecture: cellular scan. Unlike the traditional scan machine architecture, the cellular scan machine requires no scan-out pin. We introduce a dynamic scan test generation algorithm, DYNASTEE, which reduces test sequence length when compared to existing static test generation algorithms for scan architectures. We also show that test sequence length can be minimized further by re-ordering the scan chain.