An efficient polynomial multiplier in GF(2m) and its application to ECC designs

In this paper we discuss approaches that allow to construct efficient polynomial multiplication units. Such multipliers are the most important components of ECC hardware accelerators. The proposed hRAIK multiplication improves energy consumption, the longest path, and required silicon area compared to state of the art approaches. We use such a core multiplier to construct an efficient sequential polynomial multiplier based on the known iterative Karatsuba method. Finally, we exploit the beneficial properties of the design to build an ECC accelerator. The design for GF(2233) requires about 1.4 mm2 cell area in a .25 μm technology and needs 80 μsec for an EC point multiplication.