The circuit design of the synergistic processor element of a CELL processor
A 32b 4-way SIMD dual-issue synergistic processor element of a CELL processor is developed with 20.9 million transistors in 14.8mm/sup 2/ using a 90nm SOI technology. CMOS static gates implement the majority of the logic. Dynamic circuits are used in critical areas, occupying 19% of the nonSRAM area...
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| creator | Takahashi, O. Cook, R. Cottier, S. Dhong, S. H. Flachs, B. Hirairi, K. Kawasumi, A. Murakami, H. Noro, H. Oh, H. Onish, S. Pille, J. Silberman, J. |
| description | A 32b 4-way SIMD dual-issue synergistic processor element of a CELL processor is developed with 20.9 million transistors in 14.8mm/sup 2/ using a 90nm SOI technology. CMOS static gates implement the majority of the logic. Dynamic circuits are used in critical areas, occupying 19% of the nonSRAM area. ISA, microarchitecture and physical implementation are tightly coupled to achieve a compact and power efficient design. Correct operation has been observed up to 5.6GHz at 1.4V supply and 56/spl deg/C. |
| doi_str_mv | 10.5555/1129601.1129619 |
| format | Conference Proceeding |
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H. ; Flachs, B. ; Hirairi, K. ; Kawasumi, A. ; Murakami, H. ; Noro, H. ; Oh, H. ; Onish, S. ; Pille, J. ; Silberman, J.</creator><creatorcontrib>Takahashi, O. ; Cook, R. ; Cottier, S. ; Dhong, S. H. ; Flachs, B. ; Hirairi, K. ; Kawasumi, A. ; Murakami, H. ; Noro, H. ; Oh, H. ; Onish, S. ; Pille, J. ; Silberman, J.</creatorcontrib><description>A 32b 4-way SIMD dual-issue synergistic processor element of a CELL processor is developed with 20.9 million transistors in 14.8mm/sup 2/ using a 90nm SOI technology. CMOS static gates implement the majority of the logic. Dynamic circuits are used in critical areas, occupying 19% of the nonSRAM area. ISA, microarchitecture and physical implementation are tightly coupled to achieve a compact and power efficient design. Correct operation has been observed up to 5.6GHz at 1.4V supply and 56/spl deg/C.</description><identifier>ISBN: 078039254X</identifier><identifier>ISBN: 9780780392540</identifier><identifier>DOI: 10.5555/1129601.1129619</identifier><language>eng</language><publisher>Washington, DC, USA: IEEE Computer Society</publisher><subject>Applied sciences ; Design. Technologies. Operation analysis. Testing ; Electronics ; Exact sciences and technology ; Hardware ; Hardware -- Hardware validation ; Hardware -- Very large scale integration design ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Semiconductor electronics. Microelectronics. Optoelectronics. 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ISA, microarchitecture and physical implementation are tightly coupled to achieve a compact and power efficient design. Correct operation has been observed up to 5.6GHz at 1.4V supply and 56/spl deg/C.</description><subject>Applied sciences</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Hardware</subject><subject>Hardware -- Hardware validation</subject><subject>Hardware -- Very large scale integration design</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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H.</au><au>Flachs, B.</au><au>Hirairi, K.</au><au>Kawasumi, A.</au><au>Murakami, H.</au><au>Noro, H.</au><au>Oh, H.</au><au>Onish, S.</au><au>Pille, J.</au><au>Silberman, J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>The circuit design of the synergistic processor element of a CELL processor</atitle><btitle>ICCAD-2005 : International Conference on Computer Aided Design, November 6-10, 2005, DoubleTree Hotel, San Jose, CA</btitle><date>2005-05-31</date><risdate>2005</risdate><spage>111</spage><epage>117</epage><pages>111-117</pages><isbn>078039254X</isbn><isbn>9780780392540</isbn><abstract>A 32b 4-way SIMD dual-issue synergistic processor element of a CELL processor is developed with 20.9 million transistors in 14.8mm/sup 2/ using a 90nm SOI technology. CMOS static gates implement the majority of the logic. Dynamic circuits are used in critical areas, occupying 19% of the nonSRAM area. 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| fulltext | fulltext |
| identifier | ISBN: 078039254X |
| ispartof | ICCAD-2005 : International Conference on Computer Aided Design, November 6-10, 2005, DoubleTree Hotel, San Jose, CA, 2005, p.111-117 |
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| language | eng |
| recordid | cdi_acm_books_10_5555_1129601_1129619_brief |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Applied sciences Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Hardware Hardware -- Hardware validation Hardware -- Very large scale integration design Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Transistors |
| title | The circuit design of the synergistic processor element of a CELL processor |
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