The circuit design of the synergistic processor element of a CELL processor

A 32b 4-way SIMD dual-issue synergistic processor element of a CELL processor is developed with 20.9 million transistors in 14.8mm/sup 2/ using a 90nm SOI technology. CMOS static gates implement the majority of the logic. Dynamic circuits are used in critical areas, occupying 19% of the nonSRAM area...

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Bibliographische Detailangaben
Hauptverfasser:	Takahashi, O., Cook, R., Cottier, S., Dhong, S. H., Flachs, B., Hirairi, K., Kawasumi, A., Murakami, H., Noro, H., Oh, H., Onish, S., Pille, J., Silberman, J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied sciences Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Hardware Hardware > Hardware validation Hardware > Very large scale integration design Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Transistors
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Beschreibung
Zusammenfassung:	A 32b 4-way SIMD dual-issue synergistic processor element of a CELL processor is developed with 20.9 million transistors in 14.8mm/sup 2/ using a 90nm SOI technology. CMOS static gates implement the majority of the logic. Dynamic circuits are used in critical areas, occupying 19% of the nonSRAM area. ISA, microarchitecture and physical implementation are tightly coupled to achieve a compact and power efficient design. Correct operation has been observed up to 5.6GHz at 1.4V supply and 56/spl deg/C.
DOI:	10.5555/1129601.1129619