VHDL-based design and design methodology for reusable high performance direct digital requency synthesizers

Design methodologies for high performance Direct Digital Fre-quen--cy Synthesizers (DDFS) are described. Traditional look-up tab-les (LUT) for sine and co-sine are merged with CORDIC-inter-po---la--tion into a hybrid architecture. This implements DDFS-sys-tems with high resolution without being specific to a particular tar-get technology. Amplitude constants were obtained from ma-the-matical trigonometric functions of the IEEE math_real pack-age. These constants were then written via simulation of a VHDL model into a fully synthesizable package. Systematic and detailed studies varying the synthesizers inherent parameters lead to a design optimum of the LUT/CORDIC-ra-tio, which mini-mizes power and silicon area for a given clock frequency.