Ultra-low power NEMS FPGA

Ultra-low power NEMS FPGA

In this paper, we discuss a new type of NEMS switches that can be configured to implement any 2-input logic gates (AND, OR, NAND, NOR, XOR, XNOR, NOT) in a single device structure. These devices can be used to implement FPGA where a four-input CLB requires only nine NEMS switches and at most two mec...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Han, Sijing, Sirigiri, Vijay, Saab, Daniel G., Tabib-Azar, Massood
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Applied computing > Arts and humanities > Architecture (buildings) > Computer-aided design
Applied computing > Physical sciences and engineering > Engineering > Computer-aided design
Bridge circuits
CMOS integrated circuits
design
Embedded system
Field programmable gate arrays
FPGA
Hardware > Hardware validation
Hardware > Very large scale integration design > Application-specific VLSI designs
Logic gates
Nanoelectromechanical systems
NEMS
Resistors
Routing
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Beschreibung
Zusammenfassung:In this paper, we discuss a new type of NEMS switches that can be configured to implement any 2-input logic gates (AND, OR, NAND, NOR, XOR, XNOR, NOT) in a single device structure. These devices can be used to implement FPGA where a four-input CLB requires only nine NEMS switches and at most two mechanical delays per computation. In contrast, CMOS CLBs require 150 traditional switches. By reducing the number of devices, our approach improves yield, reproducibility, speed, power and simplifies implementation.
ISSN:1092-3152
1558-2434
DOI:10.1145/2429384.2429499