Minimum register requirements for a modulo schedule
Modulo scheduling is an efficient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirements. We present a combined approach that schedules the loop operations for minimum register requirements, given a modulo...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: |
Software and its engineering
> Software organization and properties
> Contextual software domains
> Operating systems
> Communications management
Theory of computation
> Design and analysis of algorithms
> Approximation algorithms analysis
> Scheduling algorithms
|
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 84 |
|---|---|
| container_issue | |
| container_start_page | 75 |
| container_title | |
| container_volume | |
| creator | Eichenberger, Alexandre E. Davidson, Edward S. Abraham, Santosh G. |
| description | Modulo scheduling is an efficient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirements. We present a combined approach that schedules the loop operations for minimum register requirements, given a modulo reservation table. Our method determines optimal register requirements for machines with finite resources and for general dependence graphs. This method demonstrates the potential of lifetime-sensitive modulo scheduling and is useful in evaluating the performance of lifetime-sensitive modulo scheduling heuristics. |
| doi_str_mv | 10.1145/192724.192732 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>proquest_acm_b</sourceid><recordid>TN_cdi_acm_books_10_1145_192724_192732_brief</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>31291135</sourcerecordid><originalsourceid>FETCH-LOGICAL-a2082-f2d9cc3a4fd1484b642fd96b12a9f791e6fff6f2b3501cc60931e6a4c4625893</originalsourceid><addsrcrecordid>eNqNkEFLxDAQRgMiqOsevffkya6ZJE2boyzqCite9h7SdKLRtnGT9v-bpYJX5_J9DI9heITcAN0AiOoeFKuZ2JyCszNyRRtVK6hpzS_IOqVPmkdUGaWXhL_60Q_zUER892nCmMtx9hEHHKdUuBALUwyhm_tQJPuBueA1OXemT7j-zRU5PD0etrty__b8sn3Yl4bRhpWOdcpaboTrQDSilYK5TskWmFEuP4TSOScda3lFwVpJFc87I6yQrGoUX5Hb5ex3DMcZ06QHnyz2vRkxzElzYAqAV3-gsYNuQ_hKGqg-qdCLCr2oyODdv0DdRo-O_wDa-F4V</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>31291135</pqid></control><display><type>conference_proceeding</type><title>Minimum register requirements for a modulo schedule</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Eichenberger, Alexandre E. ; Davidson, Edward S. ; Abraham, Santosh G.</creator><creatorcontrib>Eichenberger, Alexandre E. ; Davidson, Edward S. ; Abraham, Santosh G.</creatorcontrib><description>Modulo scheduling is an efficient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirements. We present a combined approach that schedules the loop operations for minimum register requirements, given a modulo reservation table. Our method determines optimal register requirements for machines with finite resources and for general dependence graphs. This method demonstrates the potential of lifetime-sensitive modulo scheduling and is useful in evaluating the performance of lifetime-sensitive modulo scheduling heuristics.</description><identifier>ISBN: 0897917073</identifier><identifier>ISBN: 9780897917070</identifier><identifier>DOI: 10.1145/192724.192732</identifier><language>eng</language><publisher>New York, NY, USA: ACM</publisher><subject>Hardware -- Electronic design automation -- High-level and register-transfer level synthesis ; Hardware -- Electronic design automation -- Methodologies for EDA ; Hardware -- Integrated circuits -- Logic circuits -- Arithmetic and datapath circuits ; Hardware -- Integrated circuits -- Logic circuits -- Design modules and hierarchy ; Software and its engineering -- Software notations and tools -- Compilers ; Software and its engineering -- Software organization and properties -- Contextual software domains -- Operating systems -- Communications management ; Theory of computation -- Design and analysis of algorithms -- Approximation algorithms analysis -- Scheduling algorithms ; Theory of computation -- Design and analysis of algorithms -- Online algorithms -- Online learning algorithms -- Scheduling algorithms ; Theory of computation -- Theory and algorithms for application domains -- Machine learning theory -- Reinforcement learning -- Sequential decision making</subject><ispartof>Micro 27: International Workshop in Microarchitecture, 1994, 1994, p.75-84</ispartof><rights>1994 ACM</rights><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>309,310,780,784,789,790,27925</link.rule.ids></links><search><creatorcontrib>Eichenberger, Alexandre E.</creatorcontrib><creatorcontrib>Davidson, Edward S.</creatorcontrib><creatorcontrib>Abraham, Santosh G.</creatorcontrib><title>Minimum register requirements for a modulo schedule</title><title>Micro 27: International Workshop in Microarchitecture, 1994</title><description>Modulo scheduling is an efficient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirements. We present a combined approach that schedules the loop operations for minimum register requirements, given a modulo reservation table. Our method determines optimal register requirements for machines with finite resources and for general dependence graphs. This method demonstrates the potential of lifetime-sensitive modulo scheduling and is useful in evaluating the performance of lifetime-sensitive modulo scheduling heuristics.</description><subject>Hardware -- Electronic design automation -- High-level and register-transfer level synthesis</subject><subject>Hardware -- Electronic design automation -- Methodologies for EDA</subject><subject>Hardware -- Integrated circuits -- Logic circuits -- Arithmetic and datapath circuits</subject><subject>Hardware -- Integrated circuits -- Logic circuits -- Design modules and hierarchy</subject><subject>Software and its engineering -- Software notations and tools -- Compilers</subject><subject>Software and its engineering -- Software organization and properties -- Contextual software domains -- Operating systems -- Communications management</subject><subject>Theory of computation -- Design and analysis of algorithms -- Approximation algorithms analysis -- Scheduling algorithms</subject><subject>Theory of computation -- Design and analysis of algorithms -- Online algorithms -- Online learning algorithms -- Scheduling algorithms</subject><subject>Theory of computation -- Theory and algorithms for application domains -- Machine learning theory -- Reinforcement learning -- Sequential decision making</subject><isbn>0897917073</isbn><isbn>9780897917070</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1994</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNqNkEFLxDAQRgMiqOsevffkya6ZJE2boyzqCite9h7SdKLRtnGT9v-bpYJX5_J9DI9heITcAN0AiOoeFKuZ2JyCszNyRRtVK6hpzS_IOqVPmkdUGaWXhL_60Q_zUER892nCmMtx9hEHHKdUuBALUwyhm_tQJPuBueA1OXemT7j-zRU5PD0etrty__b8sn3Yl4bRhpWOdcpaboTrQDSilYK5TskWmFEuP4TSOScda3lFwVpJFc87I6yQrGoUX5Hb5ex3DMcZ06QHnyz2vRkxzElzYAqAV3-gsYNuQ_hKGqg-qdCLCr2oyODdv0DdRo-O_wDa-F4V</recordid><startdate>19941130</startdate><enddate>19941130</enddate><creator>Eichenberger, Alexandre E.</creator><creator>Davidson, Edward S.</creator><creator>Abraham, Santosh G.</creator><general>ACM</general><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19941130</creationdate><title>Minimum register requirements for a modulo schedule</title><author>Eichenberger, Alexandre E. ; Davidson, Edward S. ; Abraham, Santosh G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a2082-f2d9cc3a4fd1484b642fd96b12a9f791e6fff6f2b3501cc60931e6a4c4625893</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1994</creationdate><topic>Hardware -- Electronic design automation -- High-level and register-transfer level synthesis</topic><topic>Hardware -- Electronic design automation -- Methodologies for EDA</topic><topic>Hardware -- Integrated circuits -- Logic circuits -- Arithmetic and datapath circuits</topic><topic>Hardware -- Integrated circuits -- Logic circuits -- Design modules and hierarchy</topic><topic>Software and its engineering -- Software notations and tools -- Compilers</topic><topic>Software and its engineering -- Software organization and properties -- Contextual software domains -- Operating systems -- Communications management</topic><topic>Theory of computation -- Design and analysis of algorithms -- Approximation algorithms analysis -- Scheduling algorithms</topic><topic>Theory of computation -- Design and analysis of algorithms -- Online algorithms -- Online learning algorithms -- Scheduling algorithms</topic><topic>Theory of computation -- Theory and algorithms for application domains -- Machine learning theory -- Reinforcement learning -- Sequential decision making</topic><toplevel>online_resources</toplevel><creatorcontrib>Eichenberger, Alexandre E.</creatorcontrib><creatorcontrib>Davidson, Edward S.</creatorcontrib><creatorcontrib>Abraham, Santosh G.</creatorcontrib><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Eichenberger, Alexandre E.</au><au>Davidson, Edward S.</au><au>Abraham, Santosh G.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Minimum register requirements for a modulo schedule</atitle><btitle>Micro 27: International Workshop in Microarchitecture, 1994</btitle><date>1994-11-30</date><risdate>1994</risdate><spage>75</spage><epage>84</epage><pages>75-84</pages><isbn>0897917073</isbn><isbn>9780897917070</isbn><abstract>Modulo scheduling is an efficient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirements. We present a combined approach that schedules the loop operations for minimum register requirements, given a modulo reservation table. Our method determines optimal register requirements for machines with finite resources and for general dependence graphs. This method demonstrates the potential of lifetime-sensitive modulo scheduling and is useful in evaluating the performance of lifetime-sensitive modulo scheduling heuristics.</abstract><cop>New York, NY, USA</cop><pub>ACM</pub><doi>10.1145/192724.192732</doi><tpages>10</tpages><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext |
| identifier | ISBN: 0897917073 |
| ispartof | Micro 27: International Workshop in Microarchitecture, 1994, 1994, p.75-84 |
| issn | |
| language | eng |
| recordid | cdi_acm_books_10_1145_192724_192732_brief |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Hardware -- Electronic design automation -- High-level and register-transfer level synthesis Hardware -- Electronic design automation -- Methodologies for EDA Hardware -- Integrated circuits -- Logic circuits -- Arithmetic and datapath circuits Hardware -- Integrated circuits -- Logic circuits -- Design modules and hierarchy Software and its engineering -- Software notations and tools -- Compilers Software and its engineering -- Software organization and properties -- Contextual software domains -- Operating systems -- Communications management Theory of computation -- Design and analysis of algorithms -- Approximation algorithms analysis -- Scheduling algorithms Theory of computation -- Design and analysis of algorithms -- Online algorithms -- Online learning algorithms -- Scheduling algorithms Theory of computation -- Theory and algorithms for application domains -- Machine learning theory -- Reinforcement learning -- Sequential decision making |
| title | Minimum register requirements for a modulo schedule |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T15%3A50%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_acm_b&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Minimum%20register%20requirements%20for%20a%20modulo%20schedule&rft.btitle=Micro%2027:%20International%20Workshop%20in%20Microarchitecture,%201994&rft.au=Eichenberger,%20Alexandre%20E.&rft.date=1994-11-30&rft.spage=75&rft.epage=84&rft.pages=75-84&rft.isbn=0897917073&rft.isbn_list=9780897917070&rft_id=info:doi/10.1145/192724.192732&rft_dat=%3Cproquest_acm_b%3E31291135%3C/proquest_acm_b%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=31291135&rft_id=info:pmid/&rfr_iscdi=true |