CMOS scaling beyond 32nm: challenges and opportunities
This paper explores the challenges and opportunities facing CMOS process generations past the 32nm technology node. Planar and multiple-gate devices are compared and contrasted. Resistance and capacitance challenges are reviewed in relation to past history and on-going research. Key enhancers such a...
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| description | This paper explores the challenges and opportunities facing CMOS process generations past the 32nm technology node. Planar and multiple-gate devices are compared and contrasted. Resistance and capacitance challenges are reviewed in relation to past history and on-going research. Key enhancers such as high-k metal-gate (HiK-MG), substrate and channel orientation, and NMOS and PMOS strain, are discussed in relation to the challenges of the coming transistor generations. |
| doi_str_mv | 10.1145/1629911.1629996 |
| format | Conference Proceeding |
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Planar and multiple-gate devices are compared and contrasted. Resistance and capacitance challenges are reviewed in relation to past history and on-going research. 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Planar and multiple-gate devices are compared and contrasted. Resistance and capacitance challenges are reviewed in relation to past history and on-going research. Key enhancers such as high-k metal-gate (HiK-MG), substrate and channel orientation, and NMOS and PMOS strain, are discussed in relation to the challenges of the coming transistor generations.</description><subject>Capacitance</subject><subject>Capacitive sensors</subject><subject>CMOS</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Degradation</subject><subject>Doping</subject><subject>Electrostatic discharge</subject><subject>Hardware -- Integrated circuits</subject><subject>high-k</subject><subject>History</subject><subject>metal-gate</subject><subject>MOS devices</subject><subject>orientation</subject><subject>strain</subject><subject>Stress</subject><issn>0738-100X</issn><isbn>9781605584973</isbn><isbn>1605584975</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNqNkDtLxEAUhQd0YZc1tYJNSpvEe2fuPG4pwResbKGC3TBJJhLdJJLY7L83uvsDrA6cw3eKT4hzhByR9DUayYyY_yWbE5GwdWhAa0ds1alYgVUuQ4C3hVg6bYhY0lIk0_QBAIiWrNMrcVE8bZ_TqQq7tn9Py7gf-jpVsu_OxKIJuykmx1yL17vbl-Ih22zvH4ubTRYkq-8sWGJyDYBC01ClaibNXM0lsaE6cBVlKJGbYKI01gSUpoqGS1IO5kqtxeXht40x-q-x7cK491pKi0rPa35YQ9X5chg-J4_gfw34owF_NODLsY3NDFz9E1A_-gVTgw</recordid><startdate>20090726</startdate><enddate>20090726</enddate><creator>Kuhn, Kelin J.</creator><general>ACM</general><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>20090726</creationdate><title>CMOS scaling beyond 32nm</title><author>Kuhn, Kelin J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a293t-a74948f00316f4c3d94599c4944964da9ce2ab19fa6e2676a126ce69b43806e23</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Capacitance</topic><topic>Capacitive sensors</topic><topic>CMOS</topic><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Degradation</topic><topic>Doping</topic><topic>Electrostatic discharge</topic><topic>Hardware -- Integrated circuits</topic><topic>high-k</topic><topic>History</topic><topic>metal-gate</topic><topic>MOS devices</topic><topic>orientation</topic><topic>strain</topic><topic>Stress</topic><toplevel>online_resources</toplevel><creatorcontrib>Kuhn, Kelin J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kuhn, Kelin J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>CMOS scaling beyond 32nm: challenges and opportunities</atitle><btitle>2009 46th ACM/IEEE Design Automation Conference</btitle><stitle>DAC</stitle><date>2009-07-26</date><risdate>2009</risdate><spage>310</spage><epage>313</epage><pages>310-313</pages><issn>0738-100X</issn><isbn>9781605584973</isbn><isbn>1605584975</isbn><abstract>This paper explores the challenges and opportunities facing CMOS process generations past the 32nm technology node. Planar and multiple-gate devices are compared and contrasted. Resistance and capacitance challenges are reviewed in relation to past history and on-going research. Key enhancers such as high-k metal-gate (HiK-MG), substrate and channel orientation, and NMOS and PMOS strain, are discussed in relation to the challenges of the coming transistor generations.</abstract><cop>New York, NY, USA</cop><pub>ACM</pub><doi>10.1145/1629911.1629996</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0738-100X |
| ispartof | 2009 46th ACM/IEEE Design Automation Conference, 2009, p.310-313 |
| issn | 0738-100X |
| language | eng |
| recordid | cdi_acm_books_10_1145_1629911_1629996_brief |
| source | IEEE Electronic Library (IEL) |
| subjects | Capacitance Capacitive sensors CMOS CMOS process CMOS technology Degradation Doping Electrostatic discharge Hardware -- Integrated circuits high-k History metal-gate MOS devices orientation strain Stress |
| title | CMOS scaling beyond 32nm: challenges and opportunities |
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