CMOS scaling beyond 32nm: challenges and opportunities

CMOS scaling beyond 32nm: challenges and opportunities

This paper explores the challenges and opportunities facing CMOS process generations past the 32nm technology node. Planar and multiple-gate devices are compared and contrasted. Resistance and capacitance challenges are reviewed in relation to past history and on-going research. Key enhancers such a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: Kuhn, Kelin J.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Capacitance
Capacitive sensors
CMOS
CMOS process
CMOS technology
Degradation
Doping
Electrostatic discharge
Hardware > Integrated circuits
high-k
History
metal-gate
MOS devices
orientation
strain
Stress
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Beschreibung
Zusammenfassung:This paper explores the challenges and opportunities facing CMOS process generations past the 32nm technology node. Planar and multiple-gate devices are compared and contrasted. Resistance and capacitance challenges are reviewed in relation to past history and on-going research. Key enhancers such as high-k metal-gate (HiK-MG), substrate and channel orientation, and NMOS and PMOS strain, are discussed in relation to the challenges of the coming transistor generations.
ISSN:0738-100X
DOI:10.1145/1629911.1629996