Datapath generator based on gate-level symbolic layout

Datapath generator based on gate-level symbolic layout

This paper describes a new datapath generator that generates high-density mask layouts equivalent to hand-crafted ones. An entry of the generator is a hierarchical symbolic layout at the gate level. Bit-and-row-slicing technique is a key feature to realize large-size and high-density datapath genera...

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Hauptverfasser: Matsumoto, Nobu, Watanabe, Yoko, Usami, Kimiyoshi, Sugeno, Yukio, Hatada, Hiroshi, Mori, Shojiro
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Applied computing > Arts and humanities > Architecture (buildings) > Computer-aided design
Applied computing > Physical sciences and engineering > Engineering > Computer-aided design
Hardware > Electronic design automation > Physical design (EDA) > Partitioning and floorplanning
Hardware > Integrated circuits
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Zusammenfassung:This paper describes a new datapath generator that generates high-density mask layouts equivalent to hand-crafted ones. An entry of the generator is a hierarchical symbolic layout at the gate level. Bit-and-row-slicing technique is a key feature to realize large-size and high-density datapath generation. A 21K transistor datapath was generated using 1- m CMOS technology, whose density is 5.64 KTr/mm2, greater than the 5.38 KTr/mm2 of a hand-crafted datapath.
DOI:10.1145/123186.123314