A generalized interconnect model for data path synthesis

A generalized interconnect model for data path synthesis

A generalized interconnect model for data path synthesis is presented. This is a multi-level interconnect model designed for synthesis under interconnect constraints. Two novel algorithms for dynamic interconnect allocation and interconnect synthesis are also described. These algorithms help impleme...

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Bibliographische Detailangaben
Hauptverfasser: Ly, Tai A., Elwood, W. Lloyd, Girczyc, Emil F.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Hardware > Electronic design automation > Physical design (EDA) > Placement
Hardware > Electronic design automation > Physical design (EDA) > Wire routing
Hardware > Very large scale integration design
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Beschreibung
Zusammenfassung:A generalized interconnect model for data path synthesis is presented. This is a multi-level interconnect model designed for synthesis under interconnect constraints. Two novel algorithms for dynamic interconnect allocation and interconnect synthesis are also described. These algorithms help implement the generalized interconnect model in the Elf hardware compiler.
DOI:10.1145/123186.123248