Machine learning for VLSI chip design
MACHINE LEARNING TECHNIQUES FOR VLSI CHIP DESIGN This cutting-edge new volume covers the hardware architecture implementation, the software implementation approach, the efficient hardware of machine learning applications with FPGA or CMOS circuits, and many other aspects and applications of machine...
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Hoboken, NJ Beverly, MA
Wiley
2023
Hoboken, NJ Beverly, MA Scrivener Publishing 2023 |
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245 | 1 | 0 | |a Machine learning for VLSI chip design |c edited by Abhishek Kumar, Suman Lata Tripathi and K. Srinivasa Rao |
264 | 1 | |a Hoboken, NJ |a Beverly, MA |b Wiley |c 2023 | |
264 | 1 | |a Hoboken, NJ |a Beverly, MA |b Scrivener Publishing |c 2023 | |
300 | |a 1 online resource. | ||
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500 | |a Includes bibliographical references and index. - Description based on online resource; title from digital title page (viewed on August 02, 2023) | ||
520 | |a MACHINE LEARNING TECHNIQUES FOR VLSI CHIP DESIGN This cutting-edge new volume covers the hardware architecture implementation, the software implementation approach, the efficient hardware of machine learning applications with FPGA or CMOS circuits, and many other aspects and applications of machine learning techniques for VLSI chip design. Artificial intelligence (AI) and machine learning (ML) have, or will have, an impact on almost every aspect of our lives and every device that we own. AI has benefitted every industry in terms of computational speeds, accurate decision prediction, efficient machine learning (ML), and deep learning (DL) algorithms. The VLSI industry uses the electronic design automation tool (EDA), and the integration with ML helps in reducing design time and cost of production. Finding defects, bugs, and hardware Trojans in the design with ML or DL can save losses during production. Constraints to ML-DL arise when having to deal with a large set of training datasets. This book covers the learning algorithm for floor planning, routing, mask fabrication, and implementation of the computational architecture for ML-DL. The future aspect of the ML-DL algorithm is to be available in the format of an integrated circuit (IC). A user can upgrade to the new algorithm by replacing an IC. This new book mainly deals with the adaption of computation blocks like hardware accelerators and novel nano-material for them based upon their application and to create a smart solution. This exciting new volume is an invaluable reference for beginners as well as engineers, scientists, researchers, and other professionals working in the area of VLSI architecture development. | ||
650 | 0 | |a Integrated circuits |x Very large scale integration |x Design |x Data processing | |
650 | 0 | |a Machine learning | |
650 | 4 | |a Apprentissage automatique | |
650 | 4 | |a Integrated circuits ; Very large scale integration ; Design ; Data processing | |
650 | 4 | |a Machine learning | |
700 | 1 | |a Kumar, Abhishek |e HerausgeberIn |4 edt | |
700 | 1 | |a Tripathi, Suman Lata |e HerausgeberIn |4 edt | |
700 | 1 | |a Srinivasa Rau, K. |e HerausgeberIn |4 edt | |
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912 | |a ZDB-30-ORH | ||
951 | |a BO | ||
912 | |a ZDB-30-ORH | ||
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Datensatz im Suchindex
DE-BY-TUM_katkey | ZDB-30-ORH-096168102 |
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adam_text | |
any_adam_object | |
author2 | Kumar, Abhishek Tripathi, Suman Lata Srinivasa Rau, K. |
author2_role | edt edt edt |
author2_variant | a k ak s l t sl slt r k s rk rks |
author_facet | Kumar, Abhishek Tripathi, Suman Lata Srinivasa Rau, K. |
building | Verbundindex |
bvnumber | localTUM |
collection | ZDB-30-ORH |
ctrlnum | (DE-627-1)096168102 (DE-599)KEP096168102 (ORHE)9781119910398 |
dewey-full | 621.39/5 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.39/5 |
dewey-search | 621.39/5 |
dewey-sort | 3621.39 15 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
format | Electronic eBook |
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id | ZDB-30-ORH-096168102 |
illustrated | Not Illustrated |
indexdate | 2024-12-18T08:48:54Z |
institution | BVB |
isbn | 9781119910497 1119910498 9781119910480 111991048X 9781119910398 |
language | English |
open_access_boolean | |
owner | DE-91 DE-BY-TUM |
owner_facet | DE-91 DE-BY-TUM |
physical | 1 online resource. |
psigel | ZDB-30-ORH |
publishDate | 2023 |
publishDateSearch | 2023 |
publishDateSort | 2023 |
publisher | Wiley Scrivener Publishing |
record_format | marc |
spelling | Machine learning for VLSI chip design edited by Abhishek Kumar, Suman Lata Tripathi and K. Srinivasa Rao Hoboken, NJ Beverly, MA Wiley 2023 Hoboken, NJ Beverly, MA Scrivener Publishing 2023 1 online resource. Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Includes bibliographical references and index. - Description based on online resource; title from digital title page (viewed on August 02, 2023) MACHINE LEARNING TECHNIQUES FOR VLSI CHIP DESIGN This cutting-edge new volume covers the hardware architecture implementation, the software implementation approach, the efficient hardware of machine learning applications with FPGA or CMOS circuits, and many other aspects and applications of machine learning techniques for VLSI chip design. Artificial intelligence (AI) and machine learning (ML) have, or will have, an impact on almost every aspect of our lives and every device that we own. AI has benefitted every industry in terms of computational speeds, accurate decision prediction, efficient machine learning (ML), and deep learning (DL) algorithms. The VLSI industry uses the electronic design automation tool (EDA), and the integration with ML helps in reducing design time and cost of production. Finding defects, bugs, and hardware Trojans in the design with ML or DL can save losses during production. Constraints to ML-DL arise when having to deal with a large set of training datasets. This book covers the learning algorithm for floor planning, routing, mask fabrication, and implementation of the computational architecture for ML-DL. The future aspect of the ML-DL algorithm is to be available in the format of an integrated circuit (IC). A user can upgrade to the new algorithm by replacing an IC. This new book mainly deals with the adaption of computation blocks like hardware accelerators and novel nano-material for them based upon their application and to create a smart solution. This exciting new volume is an invaluable reference for beginners as well as engineers, scientists, researchers, and other professionals working in the area of VLSI architecture development. Integrated circuits Very large scale integration Design Data processing Machine learning Apprentissage automatique Integrated circuits ; Very large scale integration ; Design ; Data processing Kumar, Abhishek HerausgeberIn edt Tripathi, Suman Lata HerausgeberIn edt Srinivasa Rau, K. HerausgeberIn edt TUM01 ZDB-30-ORH TUM_PDA_ORH https://learning.oreilly.com/library/view/-/9781119910398/?ar X:ORHE Aggregator lizenzpflichtig Volltext |
spellingShingle | Machine learning for VLSI chip design Integrated circuits Very large scale integration Design Data processing Machine learning Apprentissage automatique Integrated circuits ; Very large scale integration ; Design ; Data processing |
title | Machine learning for VLSI chip design |
title_auth | Machine learning for VLSI chip design |
title_exact_search | Machine learning for VLSI chip design |
title_full | Machine learning for VLSI chip design edited by Abhishek Kumar, Suman Lata Tripathi and K. Srinivasa Rao |
title_fullStr | Machine learning for VLSI chip design edited by Abhishek Kumar, Suman Lata Tripathi and K. Srinivasa Rao |
title_full_unstemmed | Machine learning for VLSI chip design edited by Abhishek Kumar, Suman Lata Tripathi and K. Srinivasa Rao |
title_short | Machine learning for VLSI chip design |
title_sort | machine learning for vlsi chip design |
topic | Integrated circuits Very large scale integration Design Data processing Machine learning Apprentissage automatique Integrated circuits ; Very large scale integration ; Design ; Data processing |
topic_facet | Integrated circuits Very large scale integration Design Data processing Machine learning Apprentissage automatique Integrated circuits ; Very large scale integration ; Design ; Data processing |
url | https://learning.oreilly.com/library/view/-/9781119910398/?ar |
work_keys_str_mv | AT kumarabhishek machinelearningforvlsichipdesign AT tripathisumanlata machinelearningforvlsichipdesign AT srinivasarauk machinelearningforvlsichipdesign |