WRTLT 2015 VMCC ; Indian Insitute of Technology Bombay - Mumbai, India

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Datensatz im Suchindex

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adam_text Table of Contents Analysis of SRAM-Based FPGA SEU Sensitivity to EMI and TID: the need for combined tests........................¿. Juliano Benfica, Bruno Green, Leticia Bolzani Poehls, Fabian Var­ gas, Nilberto Medina, Nemitala Added, Vítor de Aguiar, Eduardo Mac­ chione, Marciiéi Da Silva, Martin Perez, Miguel Sofo Haro, Ivan Sidelnik, Jerónimo Biostein, Jose Lipovetzky and Eduardo Bezerra Mapping analysis between RTL/high-level and gate-level designs with inductive invariants on partial behaviors .......... ............. ............ ... Masahiro Fujita, Qinhao Wang and Yusuke Kimura A Framework for Verification of Hard Tied Signals of SoC................. Prokash Ghosh, Sandip Ghosh and Raghavendra Srinivas Test Circuit for Electrical Interconnect Tests of 3D ICs without Boundary Scan Flip Flops.............. ................... ......................... ............... Masaki Hashizume, Shoichi Umezu, Yuki Ikiri, Hiroyuki Yotsuyanagi and Shyue-Kung Lu A Prototype of a Hardware SAT Solver for Similar Large Instances and Its Application to Test Generation .................................................................. Tsuyoshi Iwagaki, Shoichi Ohmoto, Hideyuki Ichihara and Tomoo Inoue Power Aware 3-D IC Testing using Genetic Algorithm ................. Tanusree Kaibartta and Debesh Das A Field-Test Architecture for Circuits Configured on FPGAs ........... Sho Kano and Satoshi Ohtake Improved Synthesis of Reversible Logic Circuits..................................... Bikromadittya Mondai, Pradyut Sarkar and Susanta Chakraborty Model Checking based verification of Hardware Trustworthiness.............. Yingxin Qiu and Huawei Li BDD based PDF Testable Combinational Circuit Design............................ Toral Shah, Virendra Singh and Anzhela Matrosova A Circular BIST Architecture Using Internal Responses of Circuits for Reseeding and Extra Observation ............. .................... ....... Chung-Min Shiao, Wei- Cheng Lien and Kuen- Jong Lee Effect of Static Stress in Burn-in Environment on Yield of Complex Designs ............................................ ............. .................................. .. Ankush Srivastava, Amit Aggarwal and Rakesh Bakhshi Note on Dependable Logic Design by Ambipolar Device and Its Fault Modeling.......... ............................................. .................................................... Dan Takahashi and Masayuki Arai A Fault Diagnosis Method for a Single Universal Logical Fault Model Using Multi Cycle Capture Test Sets ................... .............. ......................... Hideyuki Takano, Hiroshi Yamazaki, Toshinori Hosokawa and Koji Yamazaki Diagnosis Pattern Generation to Distinguish Inter-Gate and Intra-Gate Faults in CMOS Logic Circuits .............................................. ........... ............. Cheng-Hung Wu, Kuen-Jong Lee and Sheng-Tze Wang A Sequence Generation Method to detect Hardware Trojan Circuits........ Masayoshi Yoshimura, Tomohiro Bouyashiki and Toshinori Hosokawa 69 ^ 80 84
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spelling WRTLT 2015 VMCC ; Indian Insitute of Technology Bombay - Mumbai, India [program committee: Ilia Polian ... ; 16th IEEE Workshop on RTL and High Level Testing - 2015]
Bombay Indian Institute of Technology 2015
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Indian Institute of Technology Bombay Sonstige oth
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spellingShingle WRTLT 2015 VMCC ; Indian Insitute of Technology Bombay - Mumbai, India
VLSI (DE-588)4117388-0 gnd
Erprobung (DE-588)4260322-5 gnd
subject_GND (DE-588)4117388-0
(DE-588)4260322-5
(DE-588)1071861417
title WRTLT 2015 VMCC ; Indian Insitute of Technology Bombay - Mumbai, India
title_auth WRTLT 2015 VMCC ; Indian Insitute of Technology Bombay - Mumbai, India
title_exact_search WRTLT 2015 VMCC ; Indian Insitute of Technology Bombay - Mumbai, India
title_full WRTLT 2015 VMCC ; Indian Insitute of Technology Bombay - Mumbai, India [program committee: Ilia Polian ... ; 16th IEEE Workshop on RTL and High Level Testing - 2015]
title_fullStr WRTLT 2015 VMCC ; Indian Insitute of Technology Bombay - Mumbai, India [program committee: Ilia Polian ... ; 16th IEEE Workshop on RTL and High Level Testing - 2015]
title_full_unstemmed WRTLT 2015 VMCC ; Indian Insitute of Technology Bombay - Mumbai, India [program committee: Ilia Polian ... ; 16th IEEE Workshop on RTL and High Level Testing - 2015]
title_short WRTLT 2015
title_sort wrtlt 2015 vmcc indian insitute of technology bombay mumbai india
title_sub VMCC ; Indian Insitute of Technology Bombay - Mumbai, India
topic VLSI (DE-588)4117388-0 gnd
Erprobung (DE-588)4260322-5 gnd
topic_facet VLSI
Erprobung
Konferenzschrift
url http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=031332581&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
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