Digital Timing Macromodeling for VLSI Design Verification

Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level s...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kong, Jeong-Taek (VerfasserIn), Overhauser, David (VerfasserIn)
Format:	Elektronisch E-Book
Sprache:	English
Veröffentlicht:	Boston, MA Springer US 1995
Schriftenreihe:	The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 319
Schlagworte:	Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer-aided engineering Electrical engineering Electronic circuits Entwurf VLSI
Online-Zugang:	DE-634 URL des Erstveröffentlichers
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!