Low Power Digital CMOS Design
Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational requirements. A comprehensive approach is t...
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| Format: | Elektronisch E-Book |
| Sprache: | English |
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Boston, MA
Springer US
1995
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| 100 | 1 | |a Chandrakasan, Anantha P. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Low Power Digital CMOS Design |c by Anantha P. Chandrakasan, Robert W. Brodersen |
| 264 | 1 | |a Boston, MA |b Springer US |c 1995 | |
| 300 | |a 1 Online-Ressource (XI, 409 p) | ||
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| 520 | |a Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational requirements. A comprehensive approach is thus required at all levels of system design, ranging from algorithms and architectures to the logic styles and the underlying technology. Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply voltages of the order of 1 V using standard CMOS technology. Several techniques can also be used to minimize the switched capacitance, including representation, optimizing signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity-driven power down, etc. The high- efficiency of DC-DC converter circuitry required for efficient, low-voltage and low-current level operation is described by Stratakos, Sullivan and Sanders. The application of various low-power techniques to a chip set for multimedia applications shows that orders-of-magnitude reduction in power consumption is possible. The book also features an analysis by Professor Meindl of the fundamental limits of power consumption achievable at all levels of the design hierarchy. Svensson, of ISI, describes emerging adiabatic switching techniques that can break the CV2f barrier and reduce the energy per computation at a fixed voltage. Srivastava, of AT&T, presents the application of aggressive shut-down techniques to microprocessor applications | ||
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Datensatz im Suchindex
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| author | Chandrakasan, Anantha P. Brodersen, Robert W. |
| author_facet | Chandrakasan, Anantha P. Brodersen, Robert W. |
| author_role | aut aut |
| author_sort | Chandrakasan, Anantha P. |
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| bvnumber | BV045185821 |
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| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
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| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4615-2325-3 |
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| id | DE-604.BV045185821 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:56Z |
| institution | BVB |
| isbn | 9781461523253 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030574998 |
| oclc_num | 1053834650 |
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| physical | 1 Online-Ressource (XI, 409 p) |
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| publishDate | 1995 |
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| spelling | Chandrakasan, Anantha P. Verfasser aut Low Power Digital CMOS Design by Anantha P. Chandrakasan, Robert W. Brodersen Boston, MA Springer US 1995 1 Online-Ressource (XI, 409 p) txt rdacontent c rdamedia cr rdacarrier Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational requirements. A comprehensive approach is thus required at all levels of system design, ranging from algorithms and architectures to the logic styles and the underlying technology. Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply voltages of the order of 1 V using standard CMOS technology. Several techniques can also be used to minimize the switched capacitance, including representation, optimizing signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity-driven power down, etc. The high- efficiency of DC-DC converter circuitry required for efficient, low-voltage and low-current level operation is described by Stratakos, Sullivan and Sanders. The application of various low-power techniques to a chip set for multimedia applications shows that orders-of-magnitude reduction in power consumption is possible. The book also features an analysis by Professor Meindl of the fundamental limits of power consumption achievable at all levels of the design hierarchy. Svensson, of ISI, describes emerging adiabatic switching techniques that can break the CV2f barrier and reduce the energy per computation at a fixed voltage. Srivastava, of AT&T, presents the application of aggressive shut-down techniques to microprocessor applications Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Entwurf (DE-588)4121208-3 gnd rswk-swf CMOS-Schaltung (DE-588)4148111-2 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf CMOS-Schaltung (DE-588)4148111-2 s VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s 1\p DE-604 Brodersen, Robert W. aut Erscheint auch als Druck-Ausgabe 9781461359845 https://doi.org/10.1007/978-1-4615-2325-3 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Chandrakasan, Anantha P. Brodersen, Robert W. Low Power Digital CMOS Design Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Entwurf (DE-588)4121208-3 gnd CMOS-Schaltung (DE-588)4148111-2 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4121208-3 (DE-588)4148111-2 (DE-588)4117388-0 |
| title | Low Power Digital CMOS Design |
| title_auth | Low Power Digital CMOS Design |
| title_exact_search | Low Power Digital CMOS Design |
| title_full | Low Power Digital CMOS Design by Anantha P. Chandrakasan, Robert W. Brodersen |
| title_fullStr | Low Power Digital CMOS Design by Anantha P. Chandrakasan, Robert W. Brodersen |
| title_full_unstemmed | Low Power Digital CMOS Design by Anantha P. Chandrakasan, Robert W. Brodersen |
| title_short | Low Power Digital CMOS Design |
| title_sort | low power digital cmos design |
| topic | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Entwurf (DE-588)4121208-3 gnd CMOS-Schaltung (DE-588)4148111-2 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Entwurf CMOS-Schaltung VLSI |
| url | https://doi.org/10.1007/978-1-4615-2325-3 |
| work_keys_str_mv | AT chandrakasanananthap lowpowerdigitalcmosdesign AT brodersenrobertw lowpowerdigitalcmosdesign |