Wafer-level testing and test during burn-in for integrated circuits
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston
Artech House
2010
|
| Schriftenreihe: | Artech House integrated microsystems series
|
| Schlagworte: | |
| Online-Zugang: | FAW01 FAW02 Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Beschreibung: | Includes bibliographical references and index Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions |
|---|---|
| Beschreibung: | 1 Online-Ressource (xv, 198 p.) |
| ISBN: | 1596939893 1596939907 9781596939899 9781596939905 |