ESD design and synthesis
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| 1. Verfasser: | |
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| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Chichester, West Sussex, U.K.
Wiley
2011
|
| Schriftenreihe: | ESD series
|
| Schlagworte: | |
| Online-Zugang: | DE-1046 DE-1047 Volltext |
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| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV043118761 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 151126s2011 xx o|||| 00||| eng d | ||
| 020 | |a 0470685719 |9 0-470-68571-9 | ||
| 020 | |a 1119991137 |9 1-119-99113-7 | ||
| 020 | |a 1119991145 |9 1-119-99114-5 | ||
| 020 | |a 1119991145 |c electronic bk. |9 1-119-99114-5 | ||
| 020 | |a 1119992656 |9 1-119-99265-6 | ||
| 020 | |a 9780470685716 |9 978-0-470-68571-6 | ||
| 020 | |a 9781119991137 |9 978-1-119-99113-7 | ||
| 020 | |a 9781119991144 |c electronic bk. |9 978-1-119-99114-4 | ||
| 020 | |a 9781119992653 |9 978-1-119-99265-3 | ||
| 035 | |a (OCoLC)764691581 | ||
| 035 | |a (DE-599)BVBBV043118761 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-1046 |a DE-1047 | ||
| 082 | 0 | |a 621.3815/2 |2 22 | |
| 100 | 1 | |a Voldman, Steven H. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a ESD |b design and synthesis |c Steven H. Voldman |
| 264 | 1 | |a Chichester, West Sussex, U.K. |b Wiley |c 2011 | |
| 300 | |a 1 Online-Ressource (xx, 270 pages) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 490 | 0 | |a ESD series | |
| 500 | |a Includes bibliographical references and index | ||
| 500 | |a "The book focuses on both fundamentals of ESD design to construct and integrate a semiconductor chip. It enables ESD engineers to build better products by exploring six key areas- 1) ESD design synthesis 2) I/O design and integration 3) semiconductor chip architecture 4) floor planning 5) power bus design and 6) ESD power clamps. The book is well organised and uses a top down approach, starting by looking at the basics. It takes a look at design synthesis, floor planning and ESD design issues. The book analyses the synthesis of device elements, also the synthesis of ESD circuits and functional circuits. In Chapter 5, the synthesis of ESD power clamps is described, followed by coverage on synthesis of power rails with I/O, ESD and pads in Chapter 6. The integration of special function circuits and special issues is helpfully included in the book before more broad ESD design methodioligies are outlined. The important areas of design rule checking, along with design verification methods, are looked at towards the end of the book, and the last chapter provides the reader with knowledge about useful design tools. In many ways this text is unique. There is currently no other book on the market that addresses ESD design synthesis and its relationaship to the characterisation of test structures and technologies. Focuses on practical design techniques, providing good design practices and rules contains essential information on chip floor-planning and architecture that has not been published in a single book before covers up-to-date technology benchmarking and characterisation uses state-of-the-art examples with detailed discussion includes end-of-chapter design and integration problems"-- | ||
| 500 | |a Machine generated contents note - 1 - ESD Design Synthesis -- - 1.1 - ESD Design Synthesis and Architecture Flow -- - 1.1.1 - Top-Down ESD Design -- - 1.1.2 - Bottom-Up ESD Design -- - 1.1.3 - Top-Down ESD Design -- Memory Semiconductor Chips -- - 1.1.4 - Top-Down ESD Design -- ASIC Design System -- - 1.2 - ESD Design -- The Signal Path and the Alternate Current Path -- - 1.3 - ESD Electrical Circuit and Schematic Architecture Concepts -- - 1.3.1 - The Ideal ESD Network and the Current -- Voltage DC Design Window -- - 1.3.2 - The ESD Design Window -- - 1.3.3 - The Ideal ESD Networks in the Frequency Domain Design Window -- - 1.4 - Mapping Semiconductor Chips and ESD Designs -- - 1.4.1 - Mapping Across Semiconductor Fabricators -- - 1.4.2 - ESD Design Mapping Across Technology Generations -- - 1.4.3 - Mapping from Bipolar Technology to CMOS Technology -- - 1.4.4 - Mapping from Digital CMOS Technology to Mixed Signal Analog -- Digital CMOS Technology -- - 1.4.5 - Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI) -- - 1.4.6 - ESD Design -- Mapping CMOS to RF CMOS Technology | ||
| 500 | |a 1.5 - ESD Chip Architecture and ESD Test Standards -- - 1.5.1 - ESD Chip Architecture and ESD Testing -- - 1.6 - ESD Testing -- - 1.6.1 - ESD Qualification Testing -- - 1.6.2 - ESD Test Models -- - 1.6.3 - ESD Characterization Testing -- - 1.6.4 - TLP Testing -- - 1.7 - ESD Chip Architecture and ESD Alternative Current Paths -- - 1.7.1 - ESD Circuits, I/O, and Cores -- - 1.7.2 - ESD Signal Pin Circuits -- - 1.7.3 - ESD Power Clamp Networks -- - 1.7.4 - ESD Rail-to-Rail Circuits -- - 1.7.5 - ESD Design and Noise -- - 1.7.6 - Internal Signal Path ESD Networks -- - 1.7.7 - Cross-Domain ESD Networks -- - 1.8 - ESD Networks, Sequencing, and Chip Architecture -- - 1.9 - ESD Design Synthesis -- Latchup-Free ESD Networks -- - 1.10 - ESD Design Concepts -- Buffering -- Inter-Device -- - 1.11 - ESD Design Concepts -- Ballasting -- Inter-Device -- - 1.12 - ESD Design Concepts -- Ballasting -- Intra-Device -- - 1.13 - ESD Design Concepts -- Distributed Load Techniques -- - 1.14 - ESD Design Concepts -- Dummy Circuits -- - 1.15 - ESD Design Concepts -- Power Supply De-Coupling -- - 1.16 - ESD Design Concepts -- Feedback Loop De-Coupling -- - 1.17 - ESD Layout and Floorplan-Related Concepts | ||
| 500 | |a 1.17.1 - Design Symmetry -- - 1.17.2 - Design Segmentation -- - 1.17.3 - ESD Design Concepts -- Utilization of Empty Space -- - 1.17.4 - ESD Design Synthesis -- Across Chip Line Width Variation (ACLV) -- - 1.17.5 - ESD Design Concepts -- Dummy Shapes -- - 1.17.6 - ESD Design Concepts -- Dummy Masks -- - 1.17.7 - ESD Design Concepts -- Adjacency -- - 1.18 - ESD Design Concepts -- Analog Circuit Techniques -- - 1.19 - ESD Design Concepts -- Wire Bonds -- - 1.20 - Design Rules -- - 1.20.1 - ESD Design Rule Checking (DRC) -- - 1.20.2 - ESD Layout vs. Schematic (LVS) -- - 1.20.3 - Electrical Resistance Checking (ERC) -- - 1.21 - Summary and Closing Comments -- - Problems -- - References -- - 2 - ESD Architecture and Floorplanning -- - 2.1 - ESD Design Floorplan -- - 2.2 - Peripheral I/O Design -- - 2.2.1 - Pad-Limited Peripheral I/O Design Architecture -- - 2.2.2 - Pad-Limited Peripheral I/O Design Architecture -- Staggered I/O -- - 2.2.3 - Core-Limited Peripheral I/O Design Architecture -- - 2.3 - Lumped ESD Power Clamp in Peripheral I/O Design Architecture -- - 2.3.1 - Lumped ESD Power Clamp in Peripheral I/O Design Architecture in the Semiconductor Chip Corners | ||
| 500 | |a 2.3.2 - Lumped ESD Power Clamp in Peripheral I/O Design Architecture -- Power Pads -- - 2.4 - Lumped ESD Power Clamp in Peripheral I/O Design Architecture -- Master/Slave ESD Power Clamp System -- - 2.5 - Array I/O -- - 2.5.1 - Array I/O -- Off-Chip Driver Banks -- - 2.5.2 - Array I/O Nibble Architecture -- - 2.5.3 - Array I/O Pair Architecture -- - 2.5.4 - Array I/O -- Fully Distributed -- - 2.6 - ESD Architecture -- Dummy Bus Architectures -- - 2.6.1 - ESD Architecture -- Dummy VDD Bus -- - 2.6.2 - ESD Architecture -- Dummy Ground (VSS) Bus -- - 2.7 - Native Voltage Power Supply Architecture -- - 2.7.1 - Single Power Supply Architecture -- - 2.8 - Mixed-Voltage Architecture -- - 2.8.1 - Mixed-Voltage Architecture -- Single Power Supply -- - 2.8.2 - Mixed-Voltage Architecture -- Dual Power Supply -- - 2.9 - Mixed-Signal Architecture -- - 2.9.1 - Mixed-Signal Architecture -- Bipolar -- - 2.9.2 - Mixed-Signal Architecture -- CMOS -- - 2.10 - Mixed-System Architecture -- Digital and Analog CMOS -- - 2.10.1 - Digital and Analog CMOS Architecture -- - 2.10.2 - Digital and Analog Floorplan -- Placement of Analog Circuits -- - 2.11 - Mixed-Signal Architecture -- Digital, Analog, and RF Architecture | ||
| 500 | |a 2.12 - Summary and Closing Comments -- - Problems -- - References -- - 3 - ESD Power Grid Design -- - 3.1 - ESD Power Grid -- - 3.1.1 - ESD Power Grid -- Key ESD Design Parameters -- - 3.1.2 - ESD and the Alternative Current Path -- The Role of ESD Power Grid Resistance -- - 3.2 - Semiconductor Chip Impedance -- - 3.3 - Interconnect Failure and Dynamic On-Resistance -- - 3.3.1 - Interconnect Dynamic On-Resistance -- - 3.3.2 - Ti/Al/Ti Interconnect Failure -- - 3.3.3 - Copper Interconnect Failure -- - 3.3.4 - Melting Temperature of Interconnect Materials -- - 3.4 - Interconnect Wire and Via Guidelines -- - 3.4.1 - Interconnect Wire and Via Guidelines for HBM ESD Events -- - 3.4.2 - Interconnect Wire and Via Guidelines for MM ESD Events -- - 3.4.3 - Interconnect Wire and Via Guidelines for CDM ESD Events -- - 3.4.4 - Interconnect Wire and Via Guidelines for HMM and IEC 61000-4-2 ESD Events -- - 3.4.5 - Wire and Via ESD Metrics -- - 3.5 - ESD Power Grid Resistance -- - 3.5.1 - Power Grid Design -- ESD Input to Power Grid Resistance -- - 3.5.2 - ESD Input to Power Grid Connections -- Across ESD Bus Resistance -- - 3.5.3 - Power Grid Design -- ESD Power Clamp to Power Grid Resistance Evaluation | ||
| 500 | |a 3.5.4 - Power Grid Design -- Resistance Evaluation -- - 3.5.5 - Power Grid Design Distribution Representation -- - 3.6 - Power Grid Layout Design -- - 3.6.1 - Power Grid Design -- Slotting of Power Grid -- - 3.6.2 - Power Grid Design -- Segmentation of Power Grids -- - 3.6.3 - Power Grid Design -- Chip Corners -- - 3.6.4 - Power Grid Design -- Stacking of Metal Levels -- - 3.6.5 - Power Grid Design -- Wiring Bays and Weaved Power Bus Designs -- - 3.7 - ESD Specification Power Grid Considerations -- - 3.7.1 - CDM Specification Power Grid and Interconnect Design Considerations -- - 3.7.2 - HMM and IEC Specification Power Grid and Interconnect Design Considerations -- - 3.8 - Power Grid Design Synthesis -- ESD Design Rule Checking Methods -- - 3.8.1 - Power Grid Design Synthesis -- ESD DRC Methods Using an ESD Virtual Design Level -- - 3.8.2 - Power Grid Design Synthesis -- ESD DRC Methods Using an ESD Interconnect Parameterized Cell -- - 3.9 - Summary and Closing Comments -- - Problems -- - References -- - 4 - ESD Power Clamps -- - 4.1 - ESD Power Clamps -- - 4.1.1 - Classification of ESD Power Clamps -- - 4.1.2 - Design Synthesis of ESD Power Clamp -- Key Design Parameters | ||
| 500 | |a 4.2 - Design Synthesis of ESD Power Clamps -- - 4.2.1 - Transient Response Frequency Trigger Element and the ESD Frequency Window -- - 4.2.2 - The ESD Power Clamp Frequency Design Window -- - 4.2.3 - Design Synthesis of ESD Power Clamp -- Voltage Triggered ESD Trigger Elements -- - 4.3 - Design Synthesis of ESD Power Clamp -- The ESD Power Clamp Shunting Element -- - 4.3.1 - ESD Power Clamp Trigger Condition vs. Shunt Failure -- - 4.3.2 - ESD Clamp Element -- Width Scaling -- - 4.3.3 - ESD Clamp Element -- On-Resistance -- - 4.3.4 - ESD Clamp Element -- Safe Operating Area -- - 4.4 - ESD Power Clamp Issues -- - 4.4.1 - ESD Power Clamp Issues -- Power-Up and Power-Down -- - 4.4.2 - ESD Power Clamp Issues -- False Triggering -- - 4.4.3 - ESD Power Clamp Issues -- Pre-Charging -- - 4.4.4 - ESD Power Clamp Issues -- Post-Charging -- - 4.5 - ESD Power Clamp Design -- - 4.5.1 - Native Power Supply RC-Triggered MOSFET ESD Power Clamp -- - 4.5.2 - Non-Native Power Supply RC-Triggered MOSFET ESD Power Clamp -- - 4.5.3 - ESD Power Clamp Networks with Improved Inverter Stage Feedback -- - 4.5.4 - ESD Power Clamp Design Synthesis -- Forward Bias Triggered ESD Power Clamps | ||
| 500 | |a 4.5.5 - ESD Power Clamp Design Synthesis -- IEC 61000-4-2 Responsive ESD Power Clamps -- - 4.5.6 - ESD Power Clamp Design Synthesis -- Pre-Charging and Post-Charging Insensitive ESD Power Clamps -- - 4.6 - ESD Power Clamp Design Synthesis -- Bipolar ESD Power Clamps -- - 4.6.1 - Bipolar ESD Power Clamps with Zener Breakdown Trigger Element -- - 4.6.2 - Bipolar ESD Power Clamps with Bipolar Transistor BVceo Breakdown Trigger Element -- - 4.6.3 - Bipolar ESD Power Clamps with BVceo Bipolar Transistor Trigger and Variable Trigger Diode String Network -- - 4.6.4 - Bipolar ESD Power Clamps with Frequency Trigger Elements -- - 4.7 - Master/Slave ESD Power Clamp Systems -- - 4.8 - Summary and Closing Comments -- - Problems -- - References -- - 5 - ESD Signal Pin Networks Design and Synthesis -- - 5.1 - ESD Signal Pin Structures -- - 5.1.1 - Classification of ESD Signal Pin Networks -- - 5.1.2 - ESD Design Synthesis of ESD Signal Devices -- Key Design Parameters -- - 5.2 - ESD Input Structures -- ESD and Bond Pads Layout -- - 5.2.1 - ESD and Bond Pad Layout and Synthesis -- - 5.2.2 - ESD Structures Between Bond Pads | ||
| 500 | |a 5.2.3 - Split I/O and Bond Pad -- - 5.2.4 - Split ESD Adjacent to Bond Pad -- - 5.2.5 - ESD Structures Partially Under Bond Pads -- - 5.2.6 - ESD Structures Under and Between the Bond Pads -- - 5.2.7 - ESD Circuits and RF Bond Pad Integration -- - 5.2.8 - RF ESD Signal Pad Structures Under Bond Pads -- - 5.3 - ESD Design Synthesis and Layout of MOSFETs -- - 5.3.1 - MOSFET Key Design Parameters -- - 5.3.2 - Single MOSFET with Silicide Block Masks -- - 5.3.3 - Series Cascode MOSFET -- - 5.3.4 - Triple-well MOSFETs | ||
| 500 | |a 5.4 - ESD Design Synthesis and Layout of Diodes -- - 5.4.1 - ESD Diode Key Design Parameters -- - 5.4.2 - ESD Design Synthesis of Dual-Diode Networks -- - 5.4.3 - ESD Design Synthesis of Diode String Networks -- - 5.4.4 - ESD Design Synthesis of Back-to-Back Diode String -- - 5.4.5 - ESD Design Synthesis for Differential Pair -- - 5.5 - ESD Design Synthesis of SCRs -- - 5.5.1 - ESD Design Synthesis of Uni-directional SCRs -- - 5.5.2 - ESD Design Synthesis of Bi-directional SCRs -- - 5.5.3 - ESD Design Synthesis of SCRs -- External Trigger Element -- - 5.6 - ESD Design Synthesis and Layout of Resistors -- - 5.6.1 - Polysilicon Resistor Design Layout -- - 5.6.2 - Diffusion Resistor Design Layout -- - 5.6.3 - P-diffusion Resistor Design Layout -- - 5.6.4 - N-diffusion Resistor Design -- - 5.6.5 - Buried Resistors -- - 5.6.6 - N-well Resistors -- - 5.7 - ESD Design Synthesis of Inductors | ||
| 500 | |a 5.8 - Summary and Closing Comments -- - Problems -- - References -- - 6 - Guard Ring Design and Synthesis -- - 6.1 - Guard Ring Design and Integration -- - 6.2 - Guard Ring Characterization -- - 6.2.1 - Guard Ring Efficiency -- - 6.2.2 - Guard Ring Theory -- A Generalized Bipolar Transistor Perspective -- - 6.2.3 - Guard Ring Theory -- A Probability of Escape Perspective -- - 6.2.4 - Guard Ring -- The Injection Ratio -- - 6.3 - Semiconductor Chip Guard Ring Seal -- - 6.4 - I/O to Core Guard Rings -- - 6.5 - I/O to I/O Guard Rings -- - 6.6 - Within I/O Guard Rings -- - 6.6.1 - Within I/O Cell Guard Ring -- - 6.6.2 - ESD-to-I/O OCD Guard Ring -- - 6.7 - ESD Signal Pin Guard Rings -- - 6.7.1 - ESD Signal Pin Guard Rings and Dual-Diode ESD Network -- - 6.8 - Library Element Guard Rings -- - 6.8.1 - N-channel MOSFET Guard Rings -- - 6.8.2 - P-channel MOSFET Guard Rings -- - 6.8.3 - RF Guard Rings -- - 6.9 - Mixed-Signal Guard Rings -- Digital to Analog -- - 6.10 - Mixed-Voltage Guard Rings -- High Voltage to Low Voltage | ||
| 500 | |a 6.10.1 - Guard Rings -- High Voltage -- - 6.11 - Passive and Active Guard Rings -- - 6.11.1 - Passive Guard Rings -- - 6.11.2 - Active Guard Rings -- - 6.12 - Trench Guard Rings -- - 6.13 - TSV Guard Rings -- - 6.14 - Guard Ring DRC -- - 6.14.1 - Internal Latchup and Guard Ring Design Rules -- - 6.14.2 - External Latchup Guard Ring Design Rules -- - 6.15 - Guard Rings and Computer Aided Design Methods -- - 6.15.1 - Built-in Guard Rings -- - 6.15.2 - Guard Ring Parameterized Cells -- - 6.15.3 - Guard Ring p-Cell SKILL Code -- - 6.15.4 - Guard Ring Resistance CAD Design Checking -- - 6.15.5 - Post-Processing Methodology of Guard Ring Modification -- - 6.16 - Summary and Closing Comments -- - Problems -- - References -- - 7 - ESD Full-Chip Design Integration and Architecture -- - 7.1 - Design Synthesis and Integration -- - 7.2 - Digital Design -- - 7.3 - Custom Design vs. Standard Cell Design -- - 7.4 - Memory ESD Design -- - 7.4.1 - DRAM Design -- - 7.4.2 - SRAM Design -- - 7.4.3 - Non-Volatile RAM ESD Design -- - 7.5 - Microprocessor ESD Design | ||
| 500 | |a 7.5.1 - 3.3 V Microprocessor with 5.0 V to 3.3 V Interface -- - 7.5.2 - 2.5 V Microprocessor with 5.0 V to 2.5 V Interface -- - 7.5.3 - 1.8 V Microprocessor with 3.3 V to 1.8 V Interface -- - 7.6 - Application-Specific Integrated Circuits -- - 7.6.1 - ASIC ESD Design -- - 7.6.2 - ASIC Design Gate Array Standard Cell I/O -- - 7.6.3 - ASIC Design System with Multiple Power Rails -- - 7.6.4 - ASIC Design System with Voltage Islands -- - 7.7 - CMOS Image Processing Chip Design -- - 7.7.1 - CMOS Image Processing Chip Design with Long/Narrow Standard Cell -- - 7.7.2 - CMOS Image Processing Chip Design with Short/Wide Standard Cell -- - 7.8 - Mixed-Signal Architecture -- - 7.8.1 - Mixed-Signal Architecture -- Digital and Analog -- - 7.8.2 - Mixed-Signal Architecture -- Digital, Analog, and RF -- - 7.9 - Summary and Closing Comments -- - Problems -- - References | ||
| 650 | 4 | |a Semiconductors / Protection | |
| 650 | 4 | |a Integrated circuits / Protection | |
| 650 | 4 | |a Electrostatics | |
| 650 | 4 | |a Analog electronic systems / Design and construction | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Circuits / General |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Semiconductors |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Solid State |2 bisacsh | |
| 650 | 7 | |a Analog electronic systems / Design and construction |2 fast | |
| 650 | 7 | |a Electrostatics |2 fast | |
| 650 | 7 | |a Integrated circuits / Protection |2 fast | |
| 650 | 7 | |a Semiconductors / Protection |2 fast | |
| 650 | 4 | |a Semiconductors |x Protection | |
| 650 | 4 | |a Integrated circuits |x Protection | |
| 650 | 4 | |a Electrostatics | |
| 650 | 4 | |a Analog electronic systems |x Design and construction | |
| 650 | 0 | 7 | |a Schutzschaltung |0 (DE-588)4180279-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Elektrostatische Entladung |0 (DE-588)4401020-5 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Elektrostatische Entladung |0 (DE-588)4401020-5 |D s |
| 689 | 0 | 1 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
| 689 | 0 | 2 | |a Schutzschaltung |0 (DE-588)4180279-2 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 856 | 4 | 0 | |u http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=391336 |x Aggregator |3 Volltext |
| 912 | |a ZDB-4-EBA | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-028542952 | |
| 966 | e | |u http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=391336 |l DE-1046 |p ZDB-4-EBA |q FAW_PDA_EBA |x Aggregator |3 Volltext | |
| 966 | e | |u http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=391336 |l DE-1047 |p ZDB-4-EBA |q FAW_PDA_EBA |x Aggregator |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1819295444848607232 |
|---|---|
| any_adam_object | |
| author | Voldman, Steven H. |
| author_facet | Voldman, Steven H. |
| author_role | aut |
| author_sort | Voldman, Steven H. |
| author_variant | s h v sh shv |
| building | Verbundindex |
| bvnumber | BV043118761 |
| collection | ZDB-4-EBA |
| ctrlnum | (OCoLC)764691581 (DE-599)BVBBV043118761 |
| dewey-full | 621.3815/2 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815/2 |
| dewey-search | 621.3815/2 |
| dewey-sort | 3621.3815 12 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>18785nam a2200877zc 4500</leader><controlfield tag="001">BV043118761</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">151126s2011 xx o|||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0470685719</subfield><subfield code="9">0-470-68571-9</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1119991137</subfield><subfield code="9">1-119-99113-7</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1119991145</subfield><subfield code="9">1-119-99114-5</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1119991145</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">1-119-99114-5</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1119992656</subfield><subfield code="9">1-119-99265-6</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780470685716</subfield><subfield code="9">978-0-470-68571-6</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781119991137</subfield><subfield code="9">978-1-119-99113-7</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781119991144</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">978-1-119-99114-4</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781119992653</subfield><subfield code="9">978-1-119-99265-3</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)764691581</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV043118761</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-1046</subfield><subfield code="a">DE-1047</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815/2</subfield><subfield code="2">22</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Voldman, Steven H.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">ESD</subfield><subfield code="b">design and synthesis</subfield><subfield code="c">Steven H. Voldman</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Chichester, West Sussex, U.K.</subfield><subfield code="b">Wiley</subfield><subfield code="c">2011</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (xx, 270 pages)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">ESD series</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references and index</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">"The book focuses on both fundamentals of ESD design to construct and integrate a semiconductor chip. It enables ESD engineers to build better products by exploring six key areas- 1) ESD design synthesis 2) I/O design and integration 3) semiconductor chip architecture 4) floor planning 5) power bus design and 6) ESD power clamps. The book is well organised and uses a top down approach, starting by looking at the basics. It takes a look at design synthesis, floor planning and ESD design issues. The book analyses the synthesis of device elements, also the synthesis of ESD circuits and functional circuits. In Chapter 5, the synthesis of ESD power clamps is described, followed by coverage on synthesis of power rails with I/O, ESD and pads in Chapter 6. The integration of special function circuits and special issues is helpfully included in the book before more broad ESD design methodioligies are outlined. The important areas of design rule checking, along with design verification methods, are looked at towards the end of the book, and the last chapter provides the reader with knowledge about useful design tools. In many ways this text is unique. There is currently no other book on the market that addresses ESD design synthesis and its relationaship to the characterisation of test structures and technologies. Focuses on practical design techniques, providing good design practices and rules contains essential information on chip floor-planning and architecture that has not been published in a single book before covers up-to-date technology benchmarking and characterisation uses state-of-the-art examples with detailed discussion includes end-of-chapter design and integration problems"--</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Machine generated contents note - 1 - ESD Design Synthesis -- - 1.1 - ESD Design Synthesis and Architecture Flow -- - 1.1.1 - Top-Down ESD Design -- - 1.1.2 - Bottom-Up ESD Design -- - 1.1.3 - Top-Down ESD Design -- Memory Semiconductor Chips -- - 1.1.4 - Top-Down ESD Design -- ASIC Design System -- - 1.2 - ESD Design -- The Signal Path and the Alternate Current Path -- - 1.3 - ESD Electrical Circuit and Schematic Architecture Concepts -- - 1.3.1 - The Ideal ESD Network and the Current -- Voltage DC Design Window -- - 1.3.2 - The ESD Design Window -- - 1.3.3 - The Ideal ESD Networks in the Frequency Domain Design Window -- - 1.4 - Mapping Semiconductor Chips and ESD Designs -- - 1.4.1 - Mapping Across Semiconductor Fabricators -- - 1.4.2 - ESD Design Mapping Across Technology Generations -- - 1.4.3 - Mapping from Bipolar Technology to CMOS Technology -- - 1.4.4 - Mapping from Digital CMOS Technology to Mixed Signal Analog -- Digital CMOS Technology -- - 1.4.5 - Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI) -- - 1.4.6 - ESD Design -- Mapping CMOS to RF CMOS Technology</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">1.5 - ESD Chip Architecture and ESD Test Standards -- - 1.5.1 - ESD Chip Architecture and ESD Testing -- - 1.6 - ESD Testing -- - 1.6.1 - ESD Qualification Testing -- - 1.6.2 - ESD Test Models -- - 1.6.3 - ESD Characterization Testing -- - 1.6.4 - TLP Testing -- - 1.7 - ESD Chip Architecture and ESD Alternative Current Paths -- - 1.7.1 - ESD Circuits, I/O, and Cores -- - 1.7.2 - ESD Signal Pin Circuits -- - 1.7.3 - ESD Power Clamp Networks -- - 1.7.4 - ESD Rail-to-Rail Circuits -- - 1.7.5 - ESD Design and Noise -- - 1.7.6 - Internal Signal Path ESD Networks -- - 1.7.7 - Cross-Domain ESD Networks -- - 1.8 - ESD Networks, Sequencing, and Chip Architecture -- - 1.9 - ESD Design Synthesis -- Latchup-Free ESD Networks -- - 1.10 - ESD Design Concepts -- Buffering -- Inter-Device -- - 1.11 - ESD Design Concepts -- Ballasting -- Inter-Device -- - 1.12 - ESD Design Concepts -- Ballasting -- Intra-Device -- - 1.13 - ESD Design Concepts -- Distributed Load Techniques -- - 1.14 - ESD Design Concepts -- Dummy Circuits -- - 1.15 - ESD Design Concepts -- Power Supply De-Coupling -- - 1.16 - ESD Design Concepts -- Feedback Loop De-Coupling -- - 1.17 - ESD Layout and Floorplan-Related Concepts</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">1.17.1 - Design Symmetry -- - 1.17.2 - Design Segmentation -- - 1.17.3 - ESD Design Concepts -- Utilization of Empty Space -- - 1.17.4 - ESD Design Synthesis -- Across Chip Line Width Variation (ACLV) -- - 1.17.5 - ESD Design Concepts -- Dummy Shapes -- - 1.17.6 - ESD Design Concepts -- Dummy Masks -- - 1.17.7 - ESD Design Concepts -- Adjacency -- - 1.18 - ESD Design Concepts -- Analog Circuit Techniques -- - 1.19 - ESD Design Concepts -- Wire Bonds -- - 1.20 - Design Rules -- - 1.20.1 - ESD Design Rule Checking (DRC) -- - 1.20.2 - ESD Layout vs. Schematic (LVS) -- - 1.20.3 - Electrical Resistance Checking (ERC) -- - 1.21 - Summary and Closing Comments -- - Problems -- - References -- - 2 - ESD Architecture and Floorplanning -- - 2.1 - ESD Design Floorplan -- - 2.2 - Peripheral I/O Design -- - 2.2.1 - Pad-Limited Peripheral I/O Design Architecture -- - 2.2.2 - Pad-Limited Peripheral I/O Design Architecture -- Staggered I/O -- - 2.2.3 - Core-Limited Peripheral I/O Design Architecture -- - 2.3 - Lumped ESD Power Clamp in Peripheral I/O Design Architecture -- - 2.3.1 - Lumped ESD Power Clamp in Peripheral I/O Design Architecture in the Semiconductor Chip Corners</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">2.3.2 - Lumped ESD Power Clamp in Peripheral I/O Design Architecture -- Power Pads -- - 2.4 - Lumped ESD Power Clamp in Peripheral I/O Design Architecture -- Master/Slave ESD Power Clamp System -- - 2.5 - Array I/O -- - 2.5.1 - Array I/O -- Off-Chip Driver Banks -- - 2.5.2 - Array I/O Nibble Architecture -- - 2.5.3 - Array I/O Pair Architecture -- - 2.5.4 - Array I/O -- Fully Distributed -- - 2.6 - ESD Architecture -- Dummy Bus Architectures -- - 2.6.1 - ESD Architecture -- Dummy VDD Bus -- - 2.6.2 - ESD Architecture -- Dummy Ground (VSS) Bus -- - 2.7 - Native Voltage Power Supply Architecture -- - 2.7.1 - Single Power Supply Architecture -- - 2.8 - Mixed-Voltage Architecture -- - 2.8.1 - Mixed-Voltage Architecture -- Single Power Supply -- - 2.8.2 - Mixed-Voltage Architecture -- Dual Power Supply -- - 2.9 - Mixed-Signal Architecture -- - 2.9.1 - Mixed-Signal Architecture -- Bipolar -- - 2.9.2 - Mixed-Signal Architecture -- CMOS -- - 2.10 - Mixed-System Architecture -- Digital and Analog CMOS -- - 2.10.1 - Digital and Analog CMOS Architecture -- - 2.10.2 - Digital and Analog Floorplan -- Placement of Analog Circuits -- - 2.11 - Mixed-Signal Architecture -- Digital, Analog, and RF Architecture</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">2.12 - Summary and Closing Comments -- - Problems -- - References -- - 3 - ESD Power Grid Design -- - 3.1 - ESD Power Grid -- - 3.1.1 - ESD Power Grid -- Key ESD Design Parameters -- - 3.1.2 - ESD and the Alternative Current Path -- The Role of ESD Power Grid Resistance -- - 3.2 - Semiconductor Chip Impedance -- - 3.3 - Interconnect Failure and Dynamic On-Resistance -- - 3.3.1 - Interconnect Dynamic On-Resistance -- - 3.3.2 - Ti/Al/Ti Interconnect Failure -- - 3.3.3 - Copper Interconnect Failure -- - 3.3.4 - Melting Temperature of Interconnect Materials -- - 3.4 - Interconnect Wire and Via Guidelines -- - 3.4.1 - Interconnect Wire and Via Guidelines for HBM ESD Events -- - 3.4.2 - Interconnect Wire and Via Guidelines for MM ESD Events -- - 3.4.3 - Interconnect Wire and Via Guidelines for CDM ESD Events -- - 3.4.4 - Interconnect Wire and Via Guidelines for HMM and IEC 61000-4-2 ESD Events -- - 3.4.5 - Wire and Via ESD Metrics -- - 3.5 - ESD Power Grid Resistance -- - 3.5.1 - Power Grid Design -- ESD Input to Power Grid Resistance -- - 3.5.2 - ESD Input to Power Grid Connections -- Across ESD Bus Resistance -- - 3.5.3 - Power Grid Design -- ESD Power Clamp to Power Grid Resistance Evaluation</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">3.5.4 - Power Grid Design -- Resistance Evaluation -- - 3.5.5 - Power Grid Design Distribution Representation -- - 3.6 - Power Grid Layout Design -- - 3.6.1 - Power Grid Design -- Slotting of Power Grid -- - 3.6.2 - Power Grid Design -- Segmentation of Power Grids -- - 3.6.3 - Power Grid Design -- Chip Corners -- - 3.6.4 - Power Grid Design -- Stacking of Metal Levels -- - 3.6.5 - Power Grid Design -- Wiring Bays and Weaved Power Bus Designs -- - 3.7 - ESD Specification Power Grid Considerations -- - 3.7.1 - CDM Specification Power Grid and Interconnect Design Considerations -- - 3.7.2 - HMM and IEC Specification Power Grid and Interconnect Design Considerations -- - 3.8 - Power Grid Design Synthesis -- ESD Design Rule Checking Methods -- - 3.8.1 - Power Grid Design Synthesis -- ESD DRC Methods Using an ESD Virtual Design Level -- - 3.8.2 - Power Grid Design Synthesis -- ESD DRC Methods Using an ESD Interconnect Parameterized Cell -- - 3.9 - Summary and Closing Comments -- - Problems -- - References -- - 4 - ESD Power Clamps -- - 4.1 - ESD Power Clamps -- - 4.1.1 - Classification of ESD Power Clamps -- - 4.1.2 - Design Synthesis of ESD Power Clamp -- Key Design Parameters</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">4.2 - Design Synthesis of ESD Power Clamps -- - 4.2.1 - Transient Response Frequency Trigger Element and the ESD Frequency Window -- - 4.2.2 - The ESD Power Clamp Frequency Design Window -- - 4.2.3 - Design Synthesis of ESD Power Clamp -- Voltage Triggered ESD Trigger Elements -- - 4.3 - Design Synthesis of ESD Power Clamp -- The ESD Power Clamp Shunting Element -- - 4.3.1 - ESD Power Clamp Trigger Condition vs. Shunt Failure -- - 4.3.2 - ESD Clamp Element -- Width Scaling -- - 4.3.3 - ESD Clamp Element -- On-Resistance -- - 4.3.4 - ESD Clamp Element -- Safe Operating Area -- - 4.4 - ESD Power Clamp Issues -- - 4.4.1 - ESD Power Clamp Issues -- Power-Up and Power-Down -- - 4.4.2 - ESD Power Clamp Issues -- False Triggering -- - 4.4.3 - ESD Power Clamp Issues -- Pre-Charging -- - 4.4.4 - ESD Power Clamp Issues -- Post-Charging -- - 4.5 - ESD Power Clamp Design -- - 4.5.1 - Native Power Supply RC-Triggered MOSFET ESD Power Clamp -- - 4.5.2 - Non-Native Power Supply RC-Triggered MOSFET ESD Power Clamp -- - 4.5.3 - ESD Power Clamp Networks with Improved Inverter Stage Feedback -- - 4.5.4 - ESD Power Clamp Design Synthesis -- Forward Bias Triggered ESD Power Clamps</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">4.5.5 - ESD Power Clamp Design Synthesis -- IEC 61000-4-2 Responsive ESD Power Clamps -- - 4.5.6 - ESD Power Clamp Design Synthesis -- Pre-Charging and Post-Charging Insensitive ESD Power Clamps -- - 4.6 - ESD Power Clamp Design Synthesis -- Bipolar ESD Power Clamps -- - 4.6.1 - Bipolar ESD Power Clamps with Zener Breakdown Trigger Element -- - 4.6.2 - Bipolar ESD Power Clamps with Bipolar Transistor BVceo Breakdown Trigger Element -- - 4.6.3 - Bipolar ESD Power Clamps with BVceo Bipolar Transistor Trigger and Variable Trigger Diode String Network -- - 4.6.4 - Bipolar ESD Power Clamps with Frequency Trigger Elements -- - 4.7 - Master/Slave ESD Power Clamp Systems -- - 4.8 - Summary and Closing Comments -- - Problems -- - References -- - 5 - ESD Signal Pin Networks Design and Synthesis -- - 5.1 - ESD Signal Pin Structures -- - 5.1.1 - Classification of ESD Signal Pin Networks -- - 5.1.2 - ESD Design Synthesis of ESD Signal Devices -- Key Design Parameters -- - 5.2 - ESD Input Structures -- ESD and Bond Pads Layout -- - 5.2.1 - ESD and Bond Pad Layout and Synthesis -- - 5.2.2 - ESD Structures Between Bond Pads</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">5.2.3 - Split I/O and Bond Pad -- - 5.2.4 - Split ESD Adjacent to Bond Pad -- - 5.2.5 - ESD Structures Partially Under Bond Pads -- - 5.2.6 - ESD Structures Under and Between the Bond Pads -- - 5.2.7 - ESD Circuits and RF Bond Pad Integration -- - 5.2.8 - RF ESD Signal Pad Structures Under Bond Pads -- - 5.3 - ESD Design Synthesis and Layout of MOSFETs -- - 5.3.1 - MOSFET Key Design Parameters -- - 5.3.2 - Single MOSFET with Silicide Block Masks -- - 5.3.3 - Series Cascode MOSFET -- - 5.3.4 - Triple-well MOSFETs</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">5.4 - ESD Design Synthesis and Layout of Diodes -- - 5.4.1 - ESD Diode Key Design Parameters -- - 5.4.2 - ESD Design Synthesis of Dual-Diode Networks -- - 5.4.3 - ESD Design Synthesis of Diode String Networks -- - 5.4.4 - ESD Design Synthesis of Back-to-Back Diode String -- - 5.4.5 - ESD Design Synthesis for Differential Pair -- - 5.5 - ESD Design Synthesis of SCRs -- - 5.5.1 - ESD Design Synthesis of Uni-directional SCRs -- - 5.5.2 - ESD Design Synthesis of Bi-directional SCRs -- - 5.5.3 - ESD Design Synthesis of SCRs -- External Trigger Element -- - 5.6 - ESD Design Synthesis and Layout of Resistors -- - 5.6.1 - Polysilicon Resistor Design Layout -- - 5.6.2 - Diffusion Resistor Design Layout -- - 5.6.3 - P-diffusion Resistor Design Layout -- - 5.6.4 - N-diffusion Resistor Design -- - 5.6.5 - Buried Resistors -- - 5.6.6 - N-well Resistors -- - 5.7 - ESD Design Synthesis of Inductors</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">5.8 - Summary and Closing Comments -- - Problems -- - References -- - 6 - Guard Ring Design and Synthesis -- - 6.1 - Guard Ring Design and Integration -- - 6.2 - Guard Ring Characterization -- - 6.2.1 - Guard Ring Efficiency -- - 6.2.2 - Guard Ring Theory -- A Generalized Bipolar Transistor Perspective -- - 6.2.3 - Guard Ring Theory -- A Probability of Escape Perspective -- - 6.2.4 - Guard Ring -- The Injection Ratio -- - 6.3 - Semiconductor Chip Guard Ring Seal -- - 6.4 - I/O to Core Guard Rings -- - 6.5 - I/O to I/O Guard Rings -- - 6.6 - Within I/O Guard Rings -- - 6.6.1 - Within I/O Cell Guard Ring -- - 6.6.2 - ESD-to-I/O OCD Guard Ring -- - 6.7 - ESD Signal Pin Guard Rings -- - 6.7.1 - ESD Signal Pin Guard Rings and Dual-Diode ESD Network -- - 6.8 - Library Element Guard Rings -- - 6.8.1 - N-channel MOSFET Guard Rings -- - 6.8.2 - P-channel MOSFET Guard Rings -- - 6.8.3 - RF Guard Rings -- - 6.9 - Mixed-Signal Guard Rings -- Digital to Analog -- - 6.10 - Mixed-Voltage Guard Rings -- High Voltage to Low Voltage</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">6.10.1 - Guard Rings -- High Voltage -- - 6.11 - Passive and Active Guard Rings -- - 6.11.1 - Passive Guard Rings -- - 6.11.2 - Active Guard Rings -- - 6.12 - Trench Guard Rings -- - 6.13 - TSV Guard Rings -- - 6.14 - Guard Ring DRC -- - 6.14.1 - Internal Latchup and Guard Ring Design Rules -- - 6.14.2 - External Latchup Guard Ring Design Rules -- - 6.15 - Guard Rings and Computer Aided Design Methods -- - 6.15.1 - Built-in Guard Rings -- - 6.15.2 - Guard Ring Parameterized Cells -- - 6.15.3 - Guard Ring p-Cell SKILL Code -- - 6.15.4 - Guard Ring Resistance CAD Design Checking -- - 6.15.5 - Post-Processing Methodology of Guard Ring Modification -- - 6.16 - Summary and Closing Comments -- - Problems -- - References -- - 7 - ESD Full-Chip Design Integration and Architecture -- - 7.1 - Design Synthesis and Integration -- - 7.2 - Digital Design -- - 7.3 - Custom Design vs. Standard Cell Design -- - 7.4 - Memory ESD Design -- - 7.4.1 - DRAM Design -- - 7.4.2 - SRAM Design -- - 7.4.3 - Non-Volatile RAM ESD Design -- - 7.5 - Microprocessor ESD Design</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">7.5.1 - 3.3 V Microprocessor with 5.0 V to 3.3 V Interface -- - 7.5.2 - 2.5 V Microprocessor with 5.0 V to 2.5 V Interface -- - 7.5.3 - 1.8 V Microprocessor with 3.3 V to 1.8 V Interface -- - 7.6 - Application-Specific Integrated Circuits -- - 7.6.1 - ASIC ESD Design -- - 7.6.2 - ASIC Design Gate Array Standard Cell I/O -- - 7.6.3 - ASIC Design System with Multiple Power Rails -- - 7.6.4 - ASIC Design System with Voltage Islands -- - 7.7 - CMOS Image Processing Chip Design -- - 7.7.1 - CMOS Image Processing Chip Design with Long/Narrow Standard Cell -- - 7.7.2 - CMOS Image Processing Chip Design with Short/Wide Standard Cell -- - 7.8 - Mixed-Signal Architecture -- - 7.8.1 - Mixed-Signal Architecture -- Digital and Analog -- - 7.8.2 - Mixed-Signal Architecture -- Digital, Analog, and RF -- - 7.9 - Summary and Closing Comments -- - Problems -- - References</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Semiconductors / Protection</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits / Protection</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrostatics</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Analog electronic systems / Design and construction</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Circuits / General</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Semiconductors</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Solid State</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Analog electronic systems / Design and construction</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Electrostatics</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Integrated circuits / Protection</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Semiconductors / Protection</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Semiconductors</subfield><subfield code="x">Protection</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Protection</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrostatics</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Analog electronic systems</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schutzschaltung</subfield><subfield code="0">(DE-588)4180279-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Elektrostatische Entladung</subfield><subfield code="0">(DE-588)4401020-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Elektrostatische Entladung</subfield><subfield code="0">(DE-588)4401020-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Schutzschaltung</subfield><subfield code="0">(DE-588)4180279-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=391336</subfield><subfield code="x">Aggregator</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-4-EBA</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-028542952</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=391336</subfield><subfield code="l">DE-1046</subfield><subfield code="p">ZDB-4-EBA</subfield><subfield code="q">FAW_PDA_EBA</subfield><subfield code="x">Aggregator</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=391336</subfield><subfield code="l">DE-1047</subfield><subfield code="p">ZDB-4-EBA</subfield><subfield code="q">FAW_PDA_EBA</subfield><subfield code="x">Aggregator</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV043118761 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-24T04:42:19Z |
| institution | BVB |
| isbn | 0470685719 1119991137 1119991145 1119992656 9780470685716 9781119991137 9781119991144 9781119992653 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-028542952 |
| oclc_num | 764691581 |
| open_access_boolean | |
| owner | DE-1046 DE-1047 |
| owner_facet | DE-1046 DE-1047 |
| physical | 1 Online-Ressource (xx, 270 pages) |
| psigel | ZDB-4-EBA ZDB-4-EBA FAW_PDA_EBA |
| publishDate | 2011 |
| publishDateSearch | 2011 |
| publishDateSort | 2011 |
| publisher | Wiley |
| record_format | marc |
| series2 | ESD series |
| spelling | Voldman, Steven H. Verfasser aut ESD design and synthesis Steven H. Voldman Chichester, West Sussex, U.K. Wiley 2011 1 Online-Ressource (xx, 270 pages) txt rdacontent c rdamedia cr rdacarrier ESD series Includes bibliographical references and index "The book focuses on both fundamentals of ESD design to construct and integrate a semiconductor chip. It enables ESD engineers to build better products by exploring six key areas- 1) ESD design synthesis 2) I/O design and integration 3) semiconductor chip architecture 4) floor planning 5) power bus design and 6) ESD power clamps. The book is well organised and uses a top down approach, starting by looking at the basics. It takes a look at design synthesis, floor planning and ESD design issues. The book analyses the synthesis of device elements, also the synthesis of ESD circuits and functional circuits. In Chapter 5, the synthesis of ESD power clamps is described, followed by coverage on synthesis of power rails with I/O, ESD and pads in Chapter 6. The integration of special function circuits and special issues is helpfully included in the book before more broad ESD design methodioligies are outlined. The important areas of design rule checking, along with design verification methods, are looked at towards the end of the book, and the last chapter provides the reader with knowledge about useful design tools. In many ways this text is unique. There is currently no other book on the market that addresses ESD design synthesis and its relationaship to the characterisation of test structures and technologies. Focuses on practical design techniques, providing good design practices and rules contains essential information on chip floor-planning and architecture that has not been published in a single book before covers up-to-date technology benchmarking and characterisation uses state-of-the-art examples with detailed discussion includes end-of-chapter design and integration problems"-- Machine generated contents note - 1 - ESD Design Synthesis -- - 1.1 - ESD Design Synthesis and Architecture Flow -- - 1.1.1 - Top-Down ESD Design -- - 1.1.2 - Bottom-Up ESD Design -- - 1.1.3 - Top-Down ESD Design -- Memory Semiconductor Chips -- - 1.1.4 - Top-Down ESD Design -- ASIC Design System -- - 1.2 - ESD Design -- The Signal Path and the Alternate Current Path -- - 1.3 - ESD Electrical Circuit and Schematic Architecture Concepts -- - 1.3.1 - The Ideal ESD Network and the Current -- Voltage DC Design Window -- - 1.3.2 - The ESD Design Window -- - 1.3.3 - The Ideal ESD Networks in the Frequency Domain Design Window -- - 1.4 - Mapping Semiconductor Chips and ESD Designs -- - 1.4.1 - Mapping Across Semiconductor Fabricators -- - 1.4.2 - ESD Design Mapping Across Technology Generations -- - 1.4.3 - Mapping from Bipolar Technology to CMOS Technology -- - 1.4.4 - Mapping from Digital CMOS Technology to Mixed Signal Analog -- Digital CMOS Technology -- - 1.4.5 - Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI) -- - 1.4.6 - ESD Design -- Mapping CMOS to RF CMOS Technology 1.5 - ESD Chip Architecture and ESD Test Standards -- - 1.5.1 - ESD Chip Architecture and ESD Testing -- - 1.6 - ESD Testing -- - 1.6.1 - ESD Qualification Testing -- - 1.6.2 - ESD Test Models -- - 1.6.3 - ESD Characterization Testing -- - 1.6.4 - TLP Testing -- - 1.7 - ESD Chip Architecture and ESD Alternative Current Paths -- - 1.7.1 - ESD Circuits, I/O, and Cores -- - 1.7.2 - ESD Signal Pin Circuits -- - 1.7.3 - ESD Power Clamp Networks -- - 1.7.4 - ESD Rail-to-Rail Circuits -- - 1.7.5 - ESD Design and Noise -- - 1.7.6 - Internal Signal Path ESD Networks -- - 1.7.7 - Cross-Domain ESD Networks -- - 1.8 - ESD Networks, Sequencing, and Chip Architecture -- - 1.9 - ESD Design Synthesis -- Latchup-Free ESD Networks -- - 1.10 - ESD Design Concepts -- Buffering -- Inter-Device -- - 1.11 - ESD Design Concepts -- Ballasting -- Inter-Device -- - 1.12 - ESD Design Concepts -- Ballasting -- Intra-Device -- - 1.13 - ESD Design Concepts -- Distributed Load Techniques -- - 1.14 - ESD Design Concepts -- Dummy Circuits -- - 1.15 - ESD Design Concepts -- Power Supply De-Coupling -- - 1.16 - ESD Design Concepts -- Feedback Loop De-Coupling -- - 1.17 - ESD Layout and Floorplan-Related Concepts 1.17.1 - Design Symmetry -- - 1.17.2 - Design Segmentation -- - 1.17.3 - ESD Design Concepts -- Utilization of Empty Space -- - 1.17.4 - ESD Design Synthesis -- Across Chip Line Width Variation (ACLV) -- - 1.17.5 - ESD Design Concepts -- Dummy Shapes -- - 1.17.6 - ESD Design Concepts -- Dummy Masks -- - 1.17.7 - ESD Design Concepts -- Adjacency -- - 1.18 - ESD Design Concepts -- Analog Circuit Techniques -- - 1.19 - ESD Design Concepts -- Wire Bonds -- - 1.20 - Design Rules -- - 1.20.1 - ESD Design Rule Checking (DRC) -- - 1.20.2 - ESD Layout vs. Schematic (LVS) -- - 1.20.3 - Electrical Resistance Checking (ERC) -- - 1.21 - Summary and Closing Comments -- - Problems -- - References -- - 2 - ESD Architecture and Floorplanning -- - 2.1 - ESD Design Floorplan -- - 2.2 - Peripheral I/O Design -- - 2.2.1 - Pad-Limited Peripheral I/O Design Architecture -- - 2.2.2 - Pad-Limited Peripheral I/O Design Architecture -- Staggered I/O -- - 2.2.3 - Core-Limited Peripheral I/O Design Architecture -- - 2.3 - Lumped ESD Power Clamp in Peripheral I/O Design Architecture -- - 2.3.1 - Lumped ESD Power Clamp in Peripheral I/O Design Architecture in the Semiconductor Chip Corners 2.3.2 - Lumped ESD Power Clamp in Peripheral I/O Design Architecture -- Power Pads -- - 2.4 - Lumped ESD Power Clamp in Peripheral I/O Design Architecture -- Master/Slave ESD Power Clamp System -- - 2.5 - Array I/O -- - 2.5.1 - Array I/O -- Off-Chip Driver Banks -- - 2.5.2 - Array I/O Nibble Architecture -- - 2.5.3 - Array I/O Pair Architecture -- - 2.5.4 - Array I/O -- Fully Distributed -- - 2.6 - ESD Architecture -- Dummy Bus Architectures -- - 2.6.1 - ESD Architecture -- Dummy VDD Bus -- - 2.6.2 - ESD Architecture -- Dummy Ground (VSS) Bus -- - 2.7 - Native Voltage Power Supply Architecture -- - 2.7.1 - Single Power Supply Architecture -- - 2.8 - Mixed-Voltage Architecture -- - 2.8.1 - Mixed-Voltage Architecture -- Single Power Supply -- - 2.8.2 - Mixed-Voltage Architecture -- Dual Power Supply -- - 2.9 - Mixed-Signal Architecture -- - 2.9.1 - Mixed-Signal Architecture -- Bipolar -- - 2.9.2 - Mixed-Signal Architecture -- CMOS -- - 2.10 - Mixed-System Architecture -- Digital and Analog CMOS -- - 2.10.1 - Digital and Analog CMOS Architecture -- - 2.10.2 - Digital and Analog Floorplan -- Placement of Analog Circuits -- - 2.11 - Mixed-Signal Architecture -- Digital, Analog, and RF Architecture 2.12 - Summary and Closing Comments -- - Problems -- - References -- - 3 - ESD Power Grid Design -- - 3.1 - ESD Power Grid -- - 3.1.1 - ESD Power Grid -- Key ESD Design Parameters -- - 3.1.2 - ESD and the Alternative Current Path -- The Role of ESD Power Grid Resistance -- - 3.2 - Semiconductor Chip Impedance -- - 3.3 - Interconnect Failure and Dynamic On-Resistance -- - 3.3.1 - Interconnect Dynamic On-Resistance -- - 3.3.2 - Ti/Al/Ti Interconnect Failure -- - 3.3.3 - Copper Interconnect Failure -- - 3.3.4 - Melting Temperature of Interconnect Materials -- - 3.4 - Interconnect Wire and Via Guidelines -- - 3.4.1 - Interconnect Wire and Via Guidelines for HBM ESD Events -- - 3.4.2 - Interconnect Wire and Via Guidelines for MM ESD Events -- - 3.4.3 - Interconnect Wire and Via Guidelines for CDM ESD Events -- - 3.4.4 - Interconnect Wire and Via Guidelines for HMM and IEC 61000-4-2 ESD Events -- - 3.4.5 - Wire and Via ESD Metrics -- - 3.5 - ESD Power Grid Resistance -- - 3.5.1 - Power Grid Design -- ESD Input to Power Grid Resistance -- - 3.5.2 - ESD Input to Power Grid Connections -- Across ESD Bus Resistance -- - 3.5.3 - Power Grid Design -- ESD Power Clamp to Power Grid Resistance Evaluation 3.5.4 - Power Grid Design -- Resistance Evaluation -- - 3.5.5 - Power Grid Design Distribution Representation -- - 3.6 - Power Grid Layout Design -- - 3.6.1 - Power Grid Design -- Slotting of Power Grid -- - 3.6.2 - Power Grid Design -- Segmentation of Power Grids -- - 3.6.3 - Power Grid Design -- Chip Corners -- - 3.6.4 - Power Grid Design -- Stacking of Metal Levels -- - 3.6.5 - Power Grid Design -- Wiring Bays and Weaved Power Bus Designs -- - 3.7 - ESD Specification Power Grid Considerations -- - 3.7.1 - CDM Specification Power Grid and Interconnect Design Considerations -- - 3.7.2 - HMM and IEC Specification Power Grid and Interconnect Design Considerations -- - 3.8 - Power Grid Design Synthesis -- ESD Design Rule Checking Methods -- - 3.8.1 - Power Grid Design Synthesis -- ESD DRC Methods Using an ESD Virtual Design Level -- - 3.8.2 - Power Grid Design Synthesis -- ESD DRC Methods Using an ESD Interconnect Parameterized Cell -- - 3.9 - Summary and Closing Comments -- - Problems -- - References -- - 4 - ESD Power Clamps -- - 4.1 - ESD Power Clamps -- - 4.1.1 - Classification of ESD Power Clamps -- - 4.1.2 - Design Synthesis of ESD Power Clamp -- Key Design Parameters 4.2 - Design Synthesis of ESD Power Clamps -- - 4.2.1 - Transient Response Frequency Trigger Element and the ESD Frequency Window -- - 4.2.2 - The ESD Power Clamp Frequency Design Window -- - 4.2.3 - Design Synthesis of ESD Power Clamp -- Voltage Triggered ESD Trigger Elements -- - 4.3 - Design Synthesis of ESD Power Clamp -- The ESD Power Clamp Shunting Element -- - 4.3.1 - ESD Power Clamp Trigger Condition vs. Shunt Failure -- - 4.3.2 - ESD Clamp Element -- Width Scaling -- - 4.3.3 - ESD Clamp Element -- On-Resistance -- - 4.3.4 - ESD Clamp Element -- Safe Operating Area -- - 4.4 - ESD Power Clamp Issues -- - 4.4.1 - ESD Power Clamp Issues -- Power-Up and Power-Down -- - 4.4.2 - ESD Power Clamp Issues -- False Triggering -- - 4.4.3 - ESD Power Clamp Issues -- Pre-Charging -- - 4.4.4 - ESD Power Clamp Issues -- Post-Charging -- - 4.5 - ESD Power Clamp Design -- - 4.5.1 - Native Power Supply RC-Triggered MOSFET ESD Power Clamp -- - 4.5.2 - Non-Native Power Supply RC-Triggered MOSFET ESD Power Clamp -- - 4.5.3 - ESD Power Clamp Networks with Improved Inverter Stage Feedback -- - 4.5.4 - ESD Power Clamp Design Synthesis -- Forward Bias Triggered ESD Power Clamps 4.5.5 - ESD Power Clamp Design Synthesis -- IEC 61000-4-2 Responsive ESD Power Clamps -- - 4.5.6 - ESD Power Clamp Design Synthesis -- Pre-Charging and Post-Charging Insensitive ESD Power Clamps -- - 4.6 - ESD Power Clamp Design Synthesis -- Bipolar ESD Power Clamps -- - 4.6.1 - Bipolar ESD Power Clamps with Zener Breakdown Trigger Element -- - 4.6.2 - Bipolar ESD Power Clamps with Bipolar Transistor BVceo Breakdown Trigger Element -- - 4.6.3 - Bipolar ESD Power Clamps with BVceo Bipolar Transistor Trigger and Variable Trigger Diode String Network -- - 4.6.4 - Bipolar ESD Power Clamps with Frequency Trigger Elements -- - 4.7 - Master/Slave ESD Power Clamp Systems -- - 4.8 - Summary and Closing Comments -- - Problems -- - References -- - 5 - ESD Signal Pin Networks Design and Synthesis -- - 5.1 - ESD Signal Pin Structures -- - 5.1.1 - Classification of ESD Signal Pin Networks -- - 5.1.2 - ESD Design Synthesis of ESD Signal Devices -- Key Design Parameters -- - 5.2 - ESD Input Structures -- ESD and Bond Pads Layout -- - 5.2.1 - ESD and Bond Pad Layout and Synthesis -- - 5.2.2 - ESD Structures Between Bond Pads 5.2.3 - Split I/O and Bond Pad -- - 5.2.4 - Split ESD Adjacent to Bond Pad -- - 5.2.5 - ESD Structures Partially Under Bond Pads -- - 5.2.6 - ESD Structures Under and Between the Bond Pads -- - 5.2.7 - ESD Circuits and RF Bond Pad Integration -- - 5.2.8 - RF ESD Signal Pad Structures Under Bond Pads -- - 5.3 - ESD Design Synthesis and Layout of MOSFETs -- - 5.3.1 - MOSFET Key Design Parameters -- - 5.3.2 - Single MOSFET with Silicide Block Masks -- - 5.3.3 - Series Cascode MOSFET -- - 5.3.4 - Triple-well MOSFETs 5.4 - ESD Design Synthesis and Layout of Diodes -- - 5.4.1 - ESD Diode Key Design Parameters -- - 5.4.2 - ESD Design Synthesis of Dual-Diode Networks -- - 5.4.3 - ESD Design Synthesis of Diode String Networks -- - 5.4.4 - ESD Design Synthesis of Back-to-Back Diode String -- - 5.4.5 - ESD Design Synthesis for Differential Pair -- - 5.5 - ESD Design Synthesis of SCRs -- - 5.5.1 - ESD Design Synthesis of Uni-directional SCRs -- - 5.5.2 - ESD Design Synthesis of Bi-directional SCRs -- - 5.5.3 - ESD Design Synthesis of SCRs -- External Trigger Element -- - 5.6 - ESD Design Synthesis and Layout of Resistors -- - 5.6.1 - Polysilicon Resistor Design Layout -- - 5.6.2 - Diffusion Resistor Design Layout -- - 5.6.3 - P-diffusion Resistor Design Layout -- - 5.6.4 - N-diffusion Resistor Design -- - 5.6.5 - Buried Resistors -- - 5.6.6 - N-well Resistors -- - 5.7 - ESD Design Synthesis of Inductors 5.8 - Summary and Closing Comments -- - Problems -- - References -- - 6 - Guard Ring Design and Synthesis -- - 6.1 - Guard Ring Design and Integration -- - 6.2 - Guard Ring Characterization -- - 6.2.1 - Guard Ring Efficiency -- - 6.2.2 - Guard Ring Theory -- A Generalized Bipolar Transistor Perspective -- - 6.2.3 - Guard Ring Theory -- A Probability of Escape Perspective -- - 6.2.4 - Guard Ring -- The Injection Ratio -- - 6.3 - Semiconductor Chip Guard Ring Seal -- - 6.4 - I/O to Core Guard Rings -- - 6.5 - I/O to I/O Guard Rings -- - 6.6 - Within I/O Guard Rings -- - 6.6.1 - Within I/O Cell Guard Ring -- - 6.6.2 - ESD-to-I/O OCD Guard Ring -- - 6.7 - ESD Signal Pin Guard Rings -- - 6.7.1 - ESD Signal Pin Guard Rings and Dual-Diode ESD Network -- - 6.8 - Library Element Guard Rings -- - 6.8.1 - N-channel MOSFET Guard Rings -- - 6.8.2 - P-channel MOSFET Guard Rings -- - 6.8.3 - RF Guard Rings -- - 6.9 - Mixed-Signal Guard Rings -- Digital to Analog -- - 6.10 - Mixed-Voltage Guard Rings -- High Voltage to Low Voltage 6.10.1 - Guard Rings -- High Voltage -- - 6.11 - Passive and Active Guard Rings -- - 6.11.1 - Passive Guard Rings -- - 6.11.2 - Active Guard Rings -- - 6.12 - Trench Guard Rings -- - 6.13 - TSV Guard Rings -- - 6.14 - Guard Ring DRC -- - 6.14.1 - Internal Latchup and Guard Ring Design Rules -- - 6.14.2 - External Latchup Guard Ring Design Rules -- - 6.15 - Guard Rings and Computer Aided Design Methods -- - 6.15.1 - Built-in Guard Rings -- - 6.15.2 - Guard Ring Parameterized Cells -- - 6.15.3 - Guard Ring p-Cell SKILL Code -- - 6.15.4 - Guard Ring Resistance CAD Design Checking -- - 6.15.5 - Post-Processing Methodology of Guard Ring Modification -- - 6.16 - Summary and Closing Comments -- - Problems -- - References -- - 7 - ESD Full-Chip Design Integration and Architecture -- - 7.1 - Design Synthesis and Integration -- - 7.2 - Digital Design -- - 7.3 - Custom Design vs. Standard Cell Design -- - 7.4 - Memory ESD Design -- - 7.4.1 - DRAM Design -- - 7.4.2 - SRAM Design -- - 7.4.3 - Non-Volatile RAM ESD Design -- - 7.5 - Microprocessor ESD Design 7.5.1 - 3.3 V Microprocessor with 5.0 V to 3.3 V Interface -- - 7.5.2 - 2.5 V Microprocessor with 5.0 V to 2.5 V Interface -- - 7.5.3 - 1.8 V Microprocessor with 3.3 V to 1.8 V Interface -- - 7.6 - Application-Specific Integrated Circuits -- - 7.6.1 - ASIC ESD Design -- - 7.6.2 - ASIC Design Gate Array Standard Cell I/O -- - 7.6.3 - ASIC Design System with Multiple Power Rails -- - 7.6.4 - ASIC Design System with Voltage Islands -- - 7.7 - CMOS Image Processing Chip Design -- - 7.7.1 - CMOS Image Processing Chip Design with Long/Narrow Standard Cell -- - 7.7.2 - CMOS Image Processing Chip Design with Short/Wide Standard Cell -- - 7.8 - Mixed-Signal Architecture -- - 7.8.1 - Mixed-Signal Architecture -- Digital and Analog -- - 7.8.2 - Mixed-Signal Architecture -- Digital, Analog, and RF -- - 7.9 - Summary and Closing Comments -- - Problems -- - References Semiconductors / Protection Integrated circuits / Protection Electrostatics Analog electronic systems / Design and construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh TECHNOLOGY & ENGINEERING / Electronics / Semiconductors bisacsh TECHNOLOGY & ENGINEERING / Electronics / Solid State bisacsh Analog electronic systems / Design and construction fast Electrostatics fast Integrated circuits / Protection fast Semiconductors / Protection fast Semiconductors Protection Integrated circuits Protection Analog electronic systems Design and construction Schutzschaltung (DE-588)4180279-2 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Elektrostatische Entladung (DE-588)4401020-5 gnd rswk-swf Elektrostatische Entladung (DE-588)4401020-5 s Integrierte Schaltung (DE-588)4027242-4 s Schutzschaltung (DE-588)4180279-2 s 1\p DE-604 http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=391336 Aggregator Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Voldman, Steven H. ESD design and synthesis Semiconductors / Protection Integrated circuits / Protection Electrostatics Analog electronic systems / Design and construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh TECHNOLOGY & ENGINEERING / Electronics / Semiconductors bisacsh TECHNOLOGY & ENGINEERING / Electronics / Solid State bisacsh Analog electronic systems / Design and construction fast Electrostatics fast Integrated circuits / Protection fast Semiconductors / Protection fast Semiconductors Protection Integrated circuits Protection Analog electronic systems Design and construction Schutzschaltung (DE-588)4180279-2 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Elektrostatische Entladung (DE-588)4401020-5 gnd |
| subject_GND | (DE-588)4180279-2 (DE-588)4027242-4 (DE-588)4401020-5 |
| title | ESD design and synthesis |
| title_auth | ESD design and synthesis |
| title_exact_search | ESD design and synthesis |
| title_full | ESD design and synthesis Steven H. Voldman |
| title_fullStr | ESD design and synthesis Steven H. Voldman |
| title_full_unstemmed | ESD design and synthesis Steven H. Voldman |
| title_short | ESD |
| title_sort | esd design and synthesis |
| title_sub | design and synthesis |
| topic | Semiconductors / Protection Integrated circuits / Protection Electrostatics Analog electronic systems / Design and construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh TECHNOLOGY & ENGINEERING / Electronics / Semiconductors bisacsh TECHNOLOGY & ENGINEERING / Electronics / Solid State bisacsh Analog electronic systems / Design and construction fast Electrostatics fast Integrated circuits / Protection fast Semiconductors / Protection fast Semiconductors Protection Integrated circuits Protection Analog electronic systems Design and construction Schutzschaltung (DE-588)4180279-2 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Elektrostatische Entladung (DE-588)4401020-5 gnd |
| topic_facet | Semiconductors / Protection Integrated circuits / Protection Electrostatics Analog electronic systems / Design and construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / General TECHNOLOGY & ENGINEERING / Electronics / Semiconductors TECHNOLOGY & ENGINEERING / Electronics / Solid State Semiconductors Protection Integrated circuits Protection Analog electronic systems Design and construction Schutzschaltung Integrierte Schaltung Elektrostatische Entladung |
| url | http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=391336 |
| work_keys_str_mv | AT voldmanstevenh esddesignandsynthesis |