Microprocessor design using Verilog HDL
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| 1. Verfasser: | |
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| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Vernon, CT
Circuit Cellar
2012
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MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV039979485 | ||
| 003 | DE-604 | ||
| 005 | 20120531 | ||
| 007 | t| | ||
| 008 | 120323s2012 xx d||| |||| 00||| eng d | ||
| 020 | |a 9780963013354 |9 978-0-9630133-5-4 | ||
| 035 | |a (OCoLC)785857741 | ||
| 035 | |a (DE-599)HBZHT017132676 | ||
| 040 | |a DE-604 |b ger |e rakwb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-M347 |a DE-83 |a DE-858 | ||
| 084 | |a ST 170 |0 (DE-625)143602: |2 rvk | ||
| 084 | |a ZN 4904 |0 (DE-625)157419: |2 rvk | ||
| 100 | 1 | |a Dalrymple, Monte |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Microprocessor design using Verilog HDL |c by Monte Dalrymple |
| 264 | 1 | |a Vernon, CT |b Circuit Cellar |c 2012 | |
| 300 | |a 337 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-024836852 | |
Datensatz im Suchindex
| _version_ | 1819287534676475905 |
|---|---|
| any_adam_object | |
| author | Dalrymple, Monte |
| author_facet | Dalrymple, Monte |
| author_role | aut |
| author_sort | Dalrymple, Monte |
| author_variant | m d md |
| building | Verbundindex |
| bvnumber | BV039979485 |
| classification_rvk | ST 170 ZN 4904 |
| ctrlnum | (OCoLC)785857741 (DE-599)HBZHT017132676 |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00828nam a2200277 c 4500</leader><controlfield tag="001">BV039979485</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20120531 </controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">120323s2012 xx d||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780963013354</subfield><subfield code="9">978-0-9630133-5-4</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)785857741</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)HBZHT017132676</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-M347</subfield><subfield code="a">DE-83</subfield><subfield code="a">DE-858</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 170</subfield><subfield code="0">(DE-625)143602:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4904</subfield><subfield code="0">(DE-625)157419:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Dalrymple, Monte</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Microprocessor design using Verilog HDL</subfield><subfield code="c">by Monte Dalrymple</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Vernon, CT</subfield><subfield code="b">Circuit Cellar</subfield><subfield code="c">2012</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">337 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-024836852</subfield></datafield></record></collection> |
| id | DE-604.BV039979485 |
| illustrated | Illustrated |
| indexdate | 2024-12-24T02:36:27Z |
| institution | BVB |
| isbn | 9780963013354 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-024836852 |
| oclc_num | 785857741 |
| open_access_boolean | |
| owner | DE-M347 DE-83 DE-858 |
| owner_facet | DE-M347 DE-83 DE-858 |
| physical | 337 S. graph. Darst. |
| publishDate | 2012 |
| publishDateSearch | 2012 |
| publishDateSort | 2012 |
| publisher | Circuit Cellar |
| record_format | marc |
| spelling | Dalrymple, Monte Verfasser aut Microprocessor design using Verilog HDL by Monte Dalrymple Vernon, CT Circuit Cellar 2012 337 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier |
| spellingShingle | Dalrymple, Monte Microprocessor design using Verilog HDL |
| title | Microprocessor design using Verilog HDL |
| title_auth | Microprocessor design using Verilog HDL |
| title_exact_search | Microprocessor design using Verilog HDL |
| title_full | Microprocessor design using Verilog HDL by Monte Dalrymple |
| title_fullStr | Microprocessor design using Verilog HDL by Monte Dalrymple |
| title_full_unstemmed | Microprocessor design using Verilog HDL by Monte Dalrymple |
| title_short | Microprocessor design using Verilog HDL |
| title_sort | microprocessor design using verilog hdl |
| work_keys_str_mv | AT dalrymplemonte microprocessordesignusingveriloghdl |