Verification techniques for system-level design

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Hauptverfasser: Fujita, Masahiro (VerfasserIn), Ghosh, Indradeep (VerfasserIn), Prasad, Mukul (VerfasserIn)
Format: Buch
Sprache:English
Veröffentlicht: Amsterdam [u.a.] Elsevier, Morgan Kaufmann 2008
Schriftenreihe:The Morgan Kaufmann series in systems on silicon
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MARC

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Datensatz im Suchindex

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author Fujita, Masahiro
Ghosh, Indradeep
Prasad, Mukul
author_facet Fujita, Masahiro
Ghosh, Indradeep
Prasad, Mukul
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dewey-ones 621 - Applied physics
dewey-raw 621.3815
dewey-search 621.3815
dewey-sort 3621.3815
dewey-tens 620 - Engineering and allied operations
discipline Elektrotechnik / Elektronik / Nachrichtentechnik
format Book
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indexdate 2024-07-10T00:06:21Z
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isbn 9780123706164
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physical VIII, 240 S. graph. Darst.
publishDate 2008
publishDateSearch 2008
publishDateSort 2008
publisher Elsevier, Morgan Kaufmann
record_format marc
series2 The Morgan Kaufmann series in systems on silicon
spelling Fujita, Masahiro Verfasser aut
Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad
Amsterdam [u.a.] Elsevier, Morgan Kaufmann 2008
VIII, 240 S. graph. Darst.
txt rdacontent
n rdamedia
nc rdacarrier
The Morgan Kaufmann series in systems on silicon
Transferred to digital printing, 2011
LSI (DE-588)4168200-2 gnd rswk-swf
Hardwareverifikation (DE-588)4214982-4 gnd rswk-swf
System-on-Chip (DE-588)4740357-3 gnd rswk-swf
System-on-Chip (DE-588)4740357-3 s
LSI (DE-588)4168200-2 s
Hardwareverifikation (DE-588)4214982-4 s
DE-604
Ghosh, Indradeep Verfasser aut
Prasad, Mukul Verfasser aut
http://www.gbv.de/dms/ilmenau/toc/537756779.PDF lizenzfrei Inhaltsverzeichnis
http://www.loc.gov/catdir/enhancements/fy0808/2007028038-d.html Publisher description lizenzfrei
spellingShingle Fujita, Masahiro
Ghosh, Indradeep
Prasad, Mukul
Verification techniques for system-level design
LSI (DE-588)4168200-2 gnd
Hardwareverifikation (DE-588)4214982-4 gnd
System-on-Chip (DE-588)4740357-3 gnd
subject_GND (DE-588)4168200-2
(DE-588)4214982-4
(DE-588)4740357-3
title Verification techniques for system-level design
title_auth Verification techniques for system-level design
title_exact_search Verification techniques for system-level design
title_full Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad
title_fullStr Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad
title_full_unstemmed Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad
title_short Verification techniques for system-level design
title_sort verification techniques for system level design
topic LSI (DE-588)4168200-2 gnd
Hardwareverifikation (DE-588)4214982-4 gnd
System-on-Chip (DE-588)4740357-3 gnd
topic_facet LSI
Hardwareverifikation
System-on-Chip
url http://www.gbv.de/dms/ilmenau/toc/537756779.PDF
http://www.loc.gov/catdir/enhancements/fy0808/2007028038-d.html
work_keys_str_mv AT fujitamasahiro verificationtechniquesforsystemleveldesign
AT ghoshindradeep verificationtechniquesforsystemleveldesign
AT prasadmukul verificationtechniquesforsystemleveldesign